class A extends uvm_sequencer;
reg_model rm;
`uvm_component_utils( A )
function new( string name="A", uvm_component parent );
super.new( name );//, parent );
endfunction
virtual task configure_phase( uvm_phase phase );
super.configure_phase( phase );
$display("???????????????????? 11");
endtask
virtual task main_phase( uvm_phase phase );
uvm_status_e st;
uvm_reg_data_t value;
super.main_phase( phase );
phase.raise_objection( this );
$display("????????????????????");
rm.test_0.read( st, value, UVM_FRONTDOOR );
$display("!!!!!!!!!!!!!!!!!!!!");
$display("hhhhhhhhhhhhhhhhhhh value is %d", value);
phase.drop_objection( this );
endtask
endclass
这是你的读写操作所在嘛? uvm_sequencer 扩展一个A 来做读写操作 ?
且 reg_model 在case 0 和 A都例化了?
寄存器读写操作 一般 直接放在 testcase main_phase 进行
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