[讨论个技术问题] a 14bit 80MS/s SAR ADC with 73.6dB SNDR

zyyang_NTK

ALL文章我就不列举了，里边有点细节没太看明白，希望讨论下，谢谢
“which is a linear function of the input voltage. This is in contrast to conventional SAR ADCs with redundancy, in which the
charge on the input capacitor is altered depending upon the decision errors corrected by the redundancy. This redundancy-dependent charge residue presents a load to the input that is inherently a non-linear function of the previous sample. ”
我想知道，他说的redundancy是指刘春成的那种DAC阵列么？会有什么dependant的量呢？具体解释一下可否？

fucka03

共同學習，學習了