郑重声明：magic-semi不是收费培训公司，招聘的是正式员工和实习生

magic-semi

大家好，magic-semi是中文名字是上海实真微电子有限公司，之前发的帖子楼可能歪了，给一些人造成误解。

现郑重声明：  magic-semi不是一个收费培训公司，招聘的是正式员工和实习生。 欢迎您的加入


1. 实习生职位

Magic-semi JD forIntern

Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.   Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.

RESPONSIBILITES:

1. Responsible for developing digital designswith emphasis on backend, including Floor-plan,powerplanning, Place, CTS andRoute.

2. Work with Front-end designers to optimizetiming/area/power of the design implementation and perform static timinganalysis.

3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).

4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.

Requirements:

1.
CS/EE or background in areas related todigital or Analog chip design

2.
Known of IC backend flow.

3.
Known of timing concept.

4.
Have reading and writing skills forenglish

5.
Experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.

6.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

7.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

8.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.

9.
Good analytical and debugging skills.

Send your CV to hr@magic-semi.com if you are interested.

2.应届生

Magic-semi JD for NCG

Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.   Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.

Job Title:

Intern/NCG

RESPONSIBILITES:

1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.

2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.

3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).

4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.

Requirements:

1.
CS/EE or background in areas related todigital or analog chip design

2.
Be familiar with IC backend flow.

3.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

4.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

5.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.

6.
Good analytical and debugging skills.

Send your CV to hr@magic-semi.com if you are interested.

3. 高级工程师

Magic-semi JD forSenior Engineer

Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.   Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.

Job Title：

Senior Engineer

RESPONSIBILITES:

1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.

2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.

3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).

4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.

Requirements:

1.
CS/EE or background in areas related todigital or analog chip design

2.
3 year+ work experience.

3.
experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.

4.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

5.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

6.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.

7.
Good analytical and debugging skills.

Send your CV to hr@magic-semi.com if you are interested.

4. leader

Magic-semi JD forLeader Engineer

Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.   Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.

Job Title:

Leader Engineer

RESPONSIBILITES:

1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.

2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.

3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).

4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.

Requirements:

1.
CS/EE or background in areas related todigital or analog chip design

2.
7 year+ work experience for IC backend.

3.
Experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.

4.
Have experience for project management.

5.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

6.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

7.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.

8.
Good analytical and debugging skills.

9.
Self-motivated and good team player.

Send your CV to hr@magic-semi.com if you are interested.

IC老兵

还嫌Design Service公司少？ 有生存空间吗？ JD不能用中文吗，一看就是马甲外企，如此装逼？

magic-semi

回复 2# IC老兵

magic-semi 中文名上海实真微电子有限公司， 实习会在世界500强外企。 将会接触到顶尖的技术和工艺，欢迎发简历到hr@magic-semi.com

frustrate

支持新公司

chineselboy

IC老兵明察秋毫

火辣阎王

听说外包公司里大部分是实习生即在校学生，但按正式员工的价跟公司收费。
这样赚的差价钱如何体现外包公司的核心竞争力，里面的员工如何发展？
就一IC人贩子而已，自己员工和服务的公司两头骗。

magic-semi

我们招实习生的目的是想从不会教到会，这样做有意义。
我们不仅只是为了赚钱，是想招初级一点的，甚至没接触过，有基础的，从不会教到会，这样做才有意义。
而不像一些外包公司为了招人而招人。

magic-semi

回复 6# 火辣阎王


    什么叫两头骗，我们招的所有人都是要经过公司的面试的，简历是递上去的。
跟员工也是达成一致的。

希望不知道详细情况的同学不要乱发言，谢谢

打假315

实习生还是要慎重选择，在正规的招聘信息中寻找，不能被骗了

IC老兵

我们招实习生的目的是想从不会教到会，这样做有意义。
我们不仅只是为了赚钱，是想招初级一点的，甚至没接 ...
magic-semi 发表于 2016-6-7 00:20

                               
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实话实说不丢人，胡说八道才可恶！ 你们到底做什么，设计服务还是技术培训？ 应该Synapse模式一样“IC人贩子”，招来人签派遣合同，直接安排到客户公司on-site, 项目做完直接layoff，然后再招下一波儿，有意思吗？