拉扎维最牛著作_A 10-Bit 500-MSs 55-mW CMOS ADC

xiaowanzi88

拉扎维最牛著作_A 10-Bit 500-MSs 55-mW CMOS ADC.pdf (1.26 MB, 下载次数: 356 )

2014-3-23 11:30 上传

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xiaowanzi88

好定西~~挺一个

lwjee

谢谢分享
Ashutosh Verma, Member, IEEE, and Behzad Razavi, Fellow, IEEE
Abstract—A pipelined ADC incorporates a digital foreground
calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a highspeed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC
achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55 mW
from a 1.2-V supply.

lwjee

谢谢分享

hezudao

学术paper, 工业界应用有很明显的缺陷

xiaowanzi88

回复 5# hezudao

缺陷在哪？大神，不妨指导一下！

markhorrow

非常感谢提供！

雨丝

工业界比这牛多了！ 特别是面积方面。
贴个工业界IP的指标吧！

 40nm SMIC Low Leakage (LL)
 No Analog Options
 1.1V Core & 2.5V I/O Supplies
 12-bit ADC
 Sampling Rate up to 250MS/s
 High-Speed SAR-based Architecture
 Differential Input Signal Range: 1.0Vppdiff
 Outstanding Dynamic Performance
o 76dB SFDR at fin=10MHz
o -75dB THD at fin=10MHz
o 63.5dB SNR at fin=10MHz
o 63.1dB SNDR at fin=10MHz
o 10.2-bit ENOB at fin=10MHz
 Stand-by and Power Down Modes
 Ultra Low Power Dissipation: Only 6mW
 Ultra Compact Die Area: Only 0.09mm2

xiaowanzi88

顶起来~~~

ralphtw

good papers !