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本帖最后由 hi_china59 于 2009-12-2 12:14 编辑
339页 Cadence 培训教程 Analog Design Environment Lecture Manual
2 rar fils
For 440页 Cadence 培训教程 Analog Design Environment Lab Manual,
Please visit the following website
http://www.eetop.cn/bbs/thread-191972-1-1.html
Table of Contents
Module 1 Introduction to ADE 5.0
Analog Design Environment
Course Objectives .. .. .. . .. 1-3
Course Outline .. .. . .. . . . .. . . .. . .. . .. .. .. 1-5
Class Schedule .. .. . .. .. .. . .. .. .. . . 1-7
Getting Help 1-9
Overview of Analog Design Environment . . 1-11
Design System Initialization Files . .. 1-13
Overview of the Design Framework II Environment .. . .. .. 1-15
Advantages of Using Design Framework II . .. 1-17
The Command Interpreter Window (CIW) .. . . . .. . 1-19
Using a Form .. . . .. . . . .. .. .. 1-21
Initializing the Design Framework II Environment .. . .. .. 1-23
IC Design Flow, Front to Back .. 1-25
The Library Manager .. .. . .. . .. . 1-27
The Library Structure .. . .. 1-29
Creating a New Library . . . .. .. . .. .. .. . . 1-31
Shared Technology Library .. .. 1-33
Technology File Stored in the Design Library .. 1-35
Design Data Management. . . .. . .. .. 1-37
Overview of Schematic Entry Flow .. .. .. . 1-39
Overview of Circuit Simulation . 1-41
Types of Circuit Simulation Analyses .. . .. . .. . .. .. .. 1-43
Summary 1-45
Labs . 1-47
Lab 1-1 Getting Started . . .. .. .. 1-47
Lab 1-2 Top-Down System Modeling .. . .. . 1-47
Module 2 Schematic Entry
Schematic Entry Flow 2-3
Contents of a Schematic . . . 2-5
Creating a New Cell view .. .. .. .. .. .. .. .. . .. 2-7
Adding Component Instances .. . . .. . . . 2-9
Updating Design Objects .. . . . 2-11
Adding Sources and Ground . .. . . .. .. 2-13
Pins . .. .. .. . .. . . .. . . . . 2-15
Wires and Wire Labels . .. .. .. . .. .. .. .. .. .. .. . . 2-17
Interconnecting Components . . 2-19
Schematic Checking . . . .. .. 2-21
Schematic Checking Rules . . .. . .. . 2-23
Component Parameter Types . . 2-25
Passing Parameters Through the Hierarchy . 2-27
Symbol Generation .. .. . . .. . . .. .. 2-29
Characteristics of an Automatically Generated Symbol 2-31
Schematic Window Icons and Accelerator Keys . . .. . 2-33
Composer Command Summary .. .. . .. .. .. .. 2-35
Bindkeys .. . 2-37
Using a Hierarchy .. .. 2-39
Labs . .. . . . . . 2-41
Lab 2-1 Schematic Entry .. .. . .. . .. . . .. . . . .. . 2-41
Lab 2-2 Symbol Creation .. . .. .. .. . . 2-41
Lab 2-3 Building the Supply Circuit . .. . .. . .. 2-41
Lab 2-4 Building the ampTest Design . .. . .. . .. 2-41
Lab Reference Material: Mouse Buttons . . .. .. .. . .. 2-43
Module 3 Analog Simulation
Overview of the Analog Design Environment .. 3-3
Important Features of the Simulation Window . .. .. . .. . . 3-5
Analog Simulation Flow .. .. .. .. .. .. .. . .. 3-7
Starting the Simulation Environment . .. .. .. . . .. . 3-9
Setting the Simulator .. . .. .. . 3-11
Setting the Model Libraries .. .. 3-13
Simulation Files . .. . .. . . .. 3-15
Setting Design Variables .. .. .. .. .. .. .. . .. .. .. 3-17
Choosing Analyses .. .. . . . .. 3-19
Choosing Analyses Details .. . . .. .. .. .. .. 3-21
Simulation Environment Options . 3-23
Simulator Options .. .. .. .. . .. . . 3-25
Probing the Schematic to Save Output Data .. .. .. 3-27
Outputs Section of Simulation Window . .. .. .. .. 3-29
Netlisting .. .. .. 3-31
Running the Simulation . .. .. . .. .. 3-33
Running Additional Simulations . . . .. .. . .. .. .. 3-35
Control of Analyses for Simulation .. .. . .. . .. .. . 3-37
Additional Options Using ADE . 3-39
Analog Default Options .. .. . . .. . .. . . 3-41
Simulation States . .. . . .. . . .. . .. .. . 3-43
Stimulus Template . . . 3-45
Save Options . . .. .. .. . .. . .. .. . . . .. 3-47
Save Defaults and Save Session . .. .. . .. .. .. . .. 3-49
Infotimes . .. . . . . .. .. . . . . 3-51
Infotimes Results . .. .. .. .. .. 3-53
Captab . . .. .. .. . .. . .. .. 3-55
Selecting the captab Option from ADE . .. .. .. 3-57
Reminder to Terminate Select "Outputs " .. .. .. .. .. 3-59
Labs . .. .. .. . . . .. . .. .. . . .. .. . .. 3-61
Lab 3-1 Running Simulation 3-61
Lab 3-2 Using the Stimulus Template .. .. .. . . . 3-61
Lab 3-3 Transient Operating Point Analysis, "infotimes" .. . . .. 3-61
Lab 3-4 Captab .. . 3-61
Module 4 Simulation Results Display Tools
Overview of Simulation Display Tools . .. .. . .. . 4-3
The Waveform Window .. 4-5
Waveform Window Features . 4-7
Direct Plot .. . .. .. . .. .. .. . .. .. .. 4-9
Snapshot .. . .. .. .. . .. . .. .. .. .. . . .. 4-11
Waveform Calculator . .. .. . .. . .. 4-13
WaveScan .. .. .. .. .. . .. 4-15
Controlling Schematic Label Displays .. 4-17
Annotating Simulation Information to the Schematic .. . 4-19
Labs . . .. .. . .. . .. .. 4-21
Lab 4-1 Displaying Results with the Waveform Window 4-21
Lab 4-2 Saving the Simulation Session . .. . 4-21
Lab 4-3 Displaying Interpreted Labels Near Schematic Components 4-21
Lab 4-4 Annotating Simulation Results to the Schematic Window 4-21
Lab Reference Material. .. . .. .. .. .. .. . .. .. . 4-23
Module 5 Analyzing Simulation Results
The Waveform Calculator. . . 5-3
Postprocessing Data with the Waveform Calculator . 5-5
Waveform Calculator, Special Functions Key . . .. .. . .. .. 5-7
Print Engine .. .. . .. .. . . . .. .. .. . : . 5-9
Pri nti ng the Resul ts . . . .. 5-11
Results Display Window . .. .. .. .. 5-13
Run Data Storage Directories . 5-15
Backing Up Simulation Data Explicitly .. .. . .. .. . . . 5-17
Selecting Results .. ... .. .. . .. .. . .. . 5-19
Setting Plotting Options . .. .. .. .. .. . . 5-21
Annotating Data to the Waveform Window 5-23
Starting the Results Browser. .. 5-25
The Results Browser . .. .. .. .. . .. .. . 5-27
Viewing Presimulation Text Data . .. . .. . . .. .. 5-29
Interactive Postprocessing Tools . . . . .. .. .. . . .. . .. 5-31
Conditional Search and Display . . . . . .. .. .. .. 5-33
Setting Up a Conditional Search . . . 5-35
The Circuit Conditions Form .. 5-37
Sensitivity Analysis . . .. .. . .. .. .. .. . 5-39
Set Up Sensitivity Analysis . 5-41
Viewing Sensitivity Results . .. .. .. .. . 5-43
Spectre Sweep Feature 5-45
Introduction to Stability Analysis .. .. .. .. .. . .. . .. . 5-47
Loop-Based Algorithm .. . .. .. .. .. .. . .. . .. . 5-49
The Device-Based Algorithm . ... .. .. . .. .. . .. . 5-51
Starting Stability Analysis . .. .. .. .. . . . 5-53
Stability Analysis Results .. . .. .. .. . .. . .. . .. . 5-55
Labs . .. . .. . .. .. .. . . .. 5-57
Lab 5-1 The Waveform Calculator .. .. . . .. .. . . .. 5-57
Lab 5-2 Managing Simulation Results .. 5-57
Lab 5-3 Managing Simulation Data with the Results Browser . 5-57
Lab 5-4 Viewing Circuit Conditions .. .. . . 5-57
Lab 5-5 Using the Spectre Sweep Features . . .. . .. . . 5-57
Lab 5-6 Stability Analysis . .. 5-57
Lab Reference Materials .. . .. .. .. .. . 5-59
Module 6 SKILL and OCEAN
Overview of SKILL and OCEAN 6-3
Introduction to SKILL .. 6-5
Using SKILL Commands .. .. .. .. .. .. . . .. . . .. . 6-7
Basic SKILL Statements . .. . .. . .. . .. .. 6-9
Parentheses and Double Quotes . 6-11
Single Quote and Question Mark . . . . . . .. 6-13
Introduction to OCEAN . .. . .. . . .. 6-15
Types of OCEAN Commands .. .. .. 6-17
Sample OCEAN Script . .. .. . .. .. . .. .. . .. .. 6-19
vi Cadence Design Systems, Inc. June 4, 2003
OCEAN Help .. 6-21
Data Access Commands 6-23
Plotting Commands . . .. .. .. .. .. . .. .. 6-25
Available OCEAN Aliases . . .. .. .. .. . 6-27
Running OCEAN Interactively .. . . . .. .. .. . . .. .. 6-29
Creating OCEAN Scripts in ADE .. .. . .. . .. . . .. .. 6-31
Loading OCEAN Scripts .. . .. . .. . . .. .. 6-33
Labs .. 6-35
Lab 6-1 Using an OCEAN Script to Run a Simple Simulation . 6-35
Lab 6-2 Measuring PSRR and CMRR with OCEAN .. .. . .. 6-35
Lab 6-3 Introduction to SKILL. .. .. . . .. .. .. . 6-35
Lab 6-4 SKILL Development Tools ... .. .. .. .. .. . .. 6-35
Module 7 Parametric Analysis
Introduction to EDFM Design Tools .. . . .. . 7-3
EDFM Tool Usage .. .. .. . . . . .. .. .. . 7-5
Overview of Parametric Analysis and Flow . . .. . .. .. .. 7-7
Parametric Analysis Methodology . . .. . .. .. . .. .. 7-9
The Parametric Analysis Environment.. .. .. .. .. .. . . .. . 7-11
Parametric Plots .. .. .. . .. . 7-13
Accessing the Parametric Analysis Data Structure .. . .. 7-15
Parametric Analysis on Model Parameters .. .. .. .. .. . .. .. . 7 -17
Parametric Analysis in OCEAN .. .. .. .. .. .. 7-19
Summary .. . . .. .. .. .. .. .. . .. .. .. . 7-21
Labs . 7-23
Lab 7-1 Running Parametric Analysis . .. .. . 7-23
Module 8 Corners Analysis
Corners Analysis Tool . . .. .. .. .. .. .. .. . 8-3
Corners Analysis Window .. 8-5
Adding a New Process . . .. .. .. 8-7
Implementing Modeling Styles .. .. . . . .. . .. .. .. 8-9
Single-Model Library Style .. . .. .. . . .. .. .. .. .. 8-11
Multiple-Model Library Style .. . .. . .. .. . . .. .. 8-13
Other Styles . .. . .. . . .. .. . . 8-15
Corners Results . . .. .. . .. .. 8-17
Corners Results Window . . . . .. . . 8-19
Labs .. .. .. . . . .. .. .. . .. .. 8-21
Lab 8-1 Using the Corners Analysis Tool .. .. .. . .. .. . 8-21
Module 9 Monte Carlo Analysis
Overview of Monte Carlo Analysis .. .. . .. .. .. . .. .. .. . .. 9-3
Simulation Using Process Distributions .. .. .. .. .. .. 9-5
Example of Monte Carlo Using Simple LPF . 9-7
Monte Carlo Analysis Environment .. .. .. .. .. .. .. 9-9
Support of Spectre Direct. . .. . . . .. .. .. .. .. .. . . .. 9-11
Spectre Direct Statistical Modeling . . . . 9-13
Statistical Modeling .. . . . . . . .. 9-15
Other Features in Monte Carlo . . .. .. .. 9-17
Monte Carlo Results Analysis .. . .. . .. . 9-19
Summary .. .. .. .. .. . .. .. . .. . .. 9-25
Labs .. .. . .. . .. . .. . 9-27
Lab 9-1 Monte Carlo Analysis .. . .. .. .. .. . 9-27
Module 10 Optimization Analysis
Introduction to the Circuit Optimizer Tool . . .. . . .. 10-3
Optimization Analysis Flow . . .. .. 10-5
Optimization Computational Flow . .. . .. . .. .. .. . 10-7
Analog Circuit Optimization Option Form .. 10-9
Optimization Algorithms .. .. . .. .. . .. .. .. .. . . .. .. 10-11
Adding Goals .. .. .. . .. . . .. . . .. . .. .. .. 10-13
Design Variables Menu . .. .. . .. .. .. .. . .. .. . .. .. 10-15
Options Menu . .. .. .. .. .. . .. . .. . 10-17
Curve Fitting .. . . . .. 10-19
Curve Fitting to User-Defined Waveforms . .. .. .. .. 10-23
Iteration History .. .. . . . .. . . .. .. . .. . .. .. 10-25
Plotting Options .. . .. . . .. . .. . .. .. 10-27
OCEAN Interface .. .. .. . . .. . .. .. 10-29
Labs .. .. . . .. .. .. . .. .. .. . .. .. 10-31
Lab 10-1 Running Optimization Analysis .. .. . .. 10-31
Module 11 Component Description Format (CDF)
CDF Overview . .. .. .. . . 11-3
Types of CD F .. . .. . .. .. .. . .. .. 11-5
Levels of the CDF .. . . 11-7
The CDF User Interface Form .. . . .. . . . . .. 11-9
Editing Component Parameters in the CDF. . .. .. .. 11-11
Editing Simulation Information in the CDF . 11-13
Summary .. .. . . . .. . .. . .. . 11-17
Labs 11-19
Lab 11-1 The CDF User Interface .. .. 11-19
Lab 11-2 CDF Effects in Simulation . . . 11-19
Module 12 Macromodels, Subcircuits, and Inline Subcircuits
Overview .. . . .. 12-3
Advantages of Inline Subcircuits .. . .. . .. 12-5
Macromode1s and Subcircuits . . .. . .. . . . 12-7
Library Requirements to Use Subcircuits . 12-9
Inline Subcircuits .. . .. .. . .. .. 12-11
Inline Subcircuit Example: Parasitic Devices .. 12-13
In1ine Subcircuit Example: Parasitic Estimation .. .. .. 12-15
Generalized Binning . . . .. .. .. . . . .. .. .. .. .. 12-17
Using Inlines with the Analog Design Environment.. . 12-19
Labs 12-21
Lab 12-1 Creating a Parasitic Transistor Model . . .. 12-21
Lab 12-2 Using Subcircuit Cells . 12-21
Lab 12-3 Adding a Subcircuit Representation .. . . .. .. 12-21
Module 13 Inherited Connections
Applications of Inherited Connections .. 13-3
Features of Inherited Connections . . .. .. . .. 13-5
Defining Inherited Connections . 13-7
Setting a Net Expression . .. .. .. .. .. .. .. . .. 13-9
Override Default with the netSet Property .. .. 13-11
Netlisting with Inherited Connections .. .. .. .. . .. .. .. .. 13-13
Evaluating Net Expressions .. 13-15
Labs . .. 13-17
Lab 13-1 Inherited Connections .. . .. 13-17
Lab 13-2 Using Inherited Connections with the ampTest Design . 13-17
Module 14 The Hierarchy Editor
Applications for the Hierarchy Editor .. .. 14-3
Overview of the Hierarchy Editor.. .. .. . .. .. .. .. .. .. 14-5
Creating a Configuration .. .. .. .. .. .. 14-7
The Hierarchy Editor Window .. .. .. .. .. . . 14-9
Selecting Views with the HED 14-11
HED Tree Format .. .. .. .. . . . 14-13
Opening a Configured Schematic .. 14-1S
Synchronizing the Configured Schematic . 14-17
Summary . 14-19
Labs .. . .. . . .. .. .. .. . .. . .. . .. 14-21
Lab 14-1 Creating a Configuration File with the Hierarchy Editor.. 14-21
Lab 14-2 Running a Simulation with Subcircuits .. .. .. .. 14-21
Lab 14-3 Rerunning Simulation with the Schematic View .. 14-21
Module 15 Overview of Parasitic Simulation
Background . .. .. .. . .. .. . .. .. .. . 1S-3
Overview of Parasitic Analysis .. .. .. .. .. .. .. . .. 1S-S
Supported Layout Software . . .. .. .. .. 1S-7
What Happens in Parasitic Simulation? . .. .. .. . . . .. 1S-9
An Actual Parasitic Simulation Flow . .. .. .. . IS-II
Summary . IS-13
Labs IS-IS
Lab IS-1 Simulating a Schematic Without Parasi tics . . .. .. IS-IS
Module 16 Assura Parasitic Simulation Flow
Assura Integration into ADE .. .. .. .. .. .. .. .. . 16-3
Assura Flow in Analog Design Environment . 16-S
Assura Design Flow .. .. . .. . . . 16-7
Design Schematic . . . .. 16-9
Design Layout .. .. .. . .. .. .. .. .. . . .. .. 16-11
Accessing the Assura Commands .. . .. .. .. . . 16-13
Run RCX in Assura .. .. .. . .. . . .. .. . . . .. . .. 16-17
Assura RCX Output .. .. .. .. .. .. . .. .. 16-19
Building av_analog_extracted .. .. 16-21
Create Test Fixture Schematic and Configuration . . .. .. . 16-23
Choose Views in Configuration .. 16-2S
Running Simulation .. .. . 16-27
Waveform Analysis .. .. . 16-29
Labs 16-31
Lab 16-1 Parasitic Simulation Flow . .. . 16-31
Appendix A Diva Parasitic Simulation Flow
Diva Parasitic Extraction A-3
Diva Design Flow with Parasi tic Simulation . .. . . . A-S
Design Schematic .. .. .. . . . A-7
Design Layout .. . . .. .. . .. . .. A-9
Extraction and LVS .. .. .. .. . . .. .. .. A-11
Building analog_extracted . . A-13
Selective Parasitic Simulation .. .. . .. .. A-IS
Backannotation .. .. .. .. .. .. .. . .. .. . .. .. . A-17
Parasitic Probing . . .. .. .. .. .. . .. .. . . .. .. A-19
Create Test Fixture Schematic and Configuration .. . . . A-21
Choose Views in Configuration . .. .. .. . .. . .. .. A-23
Running Simulation . .. .. .. .. A-2S
Waveform Analysis .. .. . .. . .. . .. . . A-27
Layout Waveform Analysis .. . . . .. .. .. .. .. A-29
Schematic Waveform Analysis .. .. . .. A-31
Labs .. .. . .. . . .. .. .. . .. . A-33
Lab A-1 Simulating a Schematic with Parasitics Using the Diva Layout Flow .. A-33
Appendix B WaveScan Display Tools
WaveS can Features . . .. . . .. . .. . . B-3
WaveScan Display .. . .. . . .. . . B-9
WaveScan "Accelerator" Keys .. .. . . .. .. . B-21
Labs . . .. . B-23
Lab B-1 Using the WaveScan Tool .. .. .. .. . . B-23
Appendix C Spectre MDL
Introduction to Spectre MDL . .. .. .. . . . .. .. .. .. . C-3
Sample MDL File .. . C-S
Basic Rules .. . . .. .. .. .. . . C-7
Scope Rules Example .. .. .. .. .. . .. .. C-9
Data Types and Operators .. . .. . .. .. .. .. . .. .. C-ll
Probe Functions .. .. . . .. .. .. . . .. . . . . . .. . .. .. C-lS
Alias . .. .. .. . .. . .. .. . .. . . . . C-17
Propagating Variables .. . . .. .. .. C-19
Using foreach Statements .. . .. .. . . .. .. .. .. C-21
Autostop .. .. .. . .. . .. . .. .. . . .. . .. . C-2S
Running Spectre MDL from UNIX .. .. C-29
Spectre MDL in OCEAN . .. . . .. . .. .. .. .. . C-33
Labs .. . .. .. .. .. .. .. .. C-3S
Lab C-l Using Spectre MDL . .. .. . .. C-3S
Appendix D Match Analysis, dcmatch
Overview of Device Mismatch .. .. . . D-3
Design Considerations .. .. .. .. . . .. .. . .. . . .. . D-5
Layout Matching .. .. D-7
Special Modeling Requirements for dcmatch . .. .. D-9
Starting the dcmatch Analysis .. .. .. .. D-ll
dcmatch Analysis Selection D-13
Labs .. . .. . . . .. . .. .. . .. . .. .. .. D-15
Lab D-l dcmatch .. D-15
Appendix E Advanced Topics in ADE
Overview of Advanced Topics . E-3
Introduction to Verilog-A .. .. .. .. .. . .. .. E-5
The Veri log-A
Module . E-7
Advantages of Verilog-A . E-9
Introduction to Mixed Signal Design Environment.. .. E-ll
Advantages of Mixed Signal Design Environment . E-13
Mixed Signal Design Environment and Verilog-A . E-15
Labs . E-17
Lab E-l Verilog-A Overview . .. .. .. .. . E-17
[ 本帖最后由 hi_china59 于 2009-9-12 10:09 编辑 ] |
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