成都海光招聘深度计算芯片设计，验证和集成工程师（北京上海成都）

igovip

成都海光深度计算部门招聘芯片设计，验证和集成工程师，在北京，上海，成都均有site，部门从事深度计算芯片的研发（7nm工艺），新成立不久，虚位以待，感兴趣的朋友请发简历至my_dipper@outlook.com，机会不错（特别是对打算回成都的朋友），欢迎邮件咨询
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ASIC Design Engineer
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Description:
- SoC front-end design, including clock, reset, power and top connection
- Responsible for RTL quality and module level synthesis
- Support DV for function verification
- Support software for driver development


Qualifications:
Must have:
- minimum 3+/6+ years of ASIC design,
- Proficient in Verilog HDL, knowledge of system architecture and design
- Solid working experience with Arm architecture and AMBA
- Familiar with front-end design flow and EDA tools
- Strong problem solving, communication skills and good team work spirit
- solid knowledge in one of the following area:
  DDR/HBM Memory controler
  PCIE design
  GFX deisgn
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Job Title: ASIC Integration Engineer
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Description:
- SoC integration
- work with IP vendor (internal/external) to analyze integration issues
- SOC level LEDA, CDC check
- SOC level synthesis, STA, constraint generation,GCA, formal and timing closure
- interface to backend team on physical design and timing closure
- interface to IP team on RTL quality
- chip quality sign-off

Qualifications:
Must have:
- minimum 3+/6+ years of ASIC design or integration experience
- solid working knowledge with front-end ASIC design flow and EDA tools (Verdi,Formality/LEC, DC, PT, Spyglass, etc.)
- proficient in Verilog HDL
- familiar with DFT structure, flow and tools
- good team work spirit  
Nice to have:
- familiar with low power flow(upf,vsi check, etc.)
- working knowledge in DFT construction and integration  

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Job Title: ASIC Verification Engineer
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Job Responsibilities:
1. Responsible for design verification of cutting edge SoC projects.
2. Participate in all SoC level function verification jobs including: SoC DV testbench and infrastructure development and maintenance
3. Create and execute SoC testplan including data-path and interrupt, security, power management, etc.
4. Implement directed and random test cases in C++/SV, as well as checkers and assertions
5. Help to maintenance and improve DV environment building flow

Requirements:
1. MS with 5+ years experience in ASIC/SoC design verification
2. Hand-on experience in all domains of complex ASIC DV flow from plan to coverage
3. knowledgeable in Verilog, C, C++ & SV/UVM development, familiar with scripting languages like Perl/shell/tcl etc.
4. Strong problem solving and communication skills, DV lead experience is a big plus
5. Knowledge on computer architecture and high-speed IP interface protocol is preferred
6. Experience in power-aware verification is preferred

老公

都没有 模拟坑的

wandola

你们要模拟的吗。。。

igovip

回复 3# wandola
这边还没有模拟的职位呢