报错提示:expecting an equal sign ('=') [SystemVerilog - 6.3.3]
class a_test_base #(type a_env) extends uvm_test;
...
endclass
Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
`uvm_component_utils(a_tets_base#(a_env))