求paper

euro_pean

有参加会议的手头有这两篇paper的大神吗？先谢了


P. Chen, X. Huang, Y.-H. Liu, M. Ding, C. Zhou, A. Ba, K. Philips, H. de Groot, and R. B. Staszewski, “Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. x–x, pp. x–x, x Sept. 2015, Graz, Austria. (accepted)

P. Chen, X.-C. Huang, and R. B. Staszewski, “Fractional spur suppression in all-digital phase-locked loops,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 2597,sec. C4L-B, pp. 1–4, 27 May 2015, Lisbon, Portugal

JoyShockley

回复 1# euro_pean


    这些论文，还没被收录到Xplore 里，目前还是查不到的。

    C4L-B02-2597.pdf (1.2 MB , 下载次数: 104 )

2015-6-30 18:33 上传

点击文件名下载附件

这是第二篇

harry1862pd

JoyShockley 真是个好同志啊

euro_pean

回复 2# JoyShockley


    多谢，发现你原来是这个组的

Lianbo Wu        MSc. thesis defense: 2014-10-28        An Ultra-Low-Power ADPLL for BLE Applications        NXP, Eindhoven, NL
Peng Chen        MSc. thesis defense: 2014-09-18        DTC and TDC IC Design for Ultra-Low-Power ADPLL        Huawei, Eindhoven, NL
Bindi Wang        MSc. thesis defense: 2013-12-20        Edge-prediction DTC and Self-gating TDC Design for Ultra Low Power All Digital PLL

这几篇硕士论文大神有吗？

JoyShockley

回复 4# euro_pean


    如果在TU Delft网站，下载不到，就是处在保密期。如果不在保密期，可以直接下载的

AnnieSEU

同求第一篇