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Supplements for R.J Baker's CMOS Circuit Design(SPICE&Cadence Model etc...)

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发表于 2008-2-13 23:19:37 | 显示全部楼层 |阅读模式

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CMOS: Circuit Design, Layout, and Simulation, Revised, 2nd Edition

                               
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Layout software and MOSIS information
Cadence Design System – Ubiquitous commercial CAD system with a generous university program
Electric VLSI Design System – free and powerful CAD system for chip design (schematics, layout, DRC, LVS, ERC, etc.)

                               
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SPICE software and MOSFET modelsThe book’s SPICE simulation examples are available in LTspice (*.asc), WinSpice (*.cir), or HSPICE (*.sp) formats.
The 50 nm and 1 mm MOSFET models are found in cmos_models.txt (see also, BSIM4 manual).

Chaps 1-10: CMOS Fundamentals
Chaps 11-15 Digital Design
Chaps 16-19 Advanced Digital Design
Chaps 20-24: Analog Design
Chaps 25-29: Advanced Analog Design


                               
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CMOS: Circuit Design, Layout, and Simulation, Revised, 2nd Edition
R. Jacob Baker, Boise State University and Micron Technology, Inc.
ISBN: 978-0-470-22941-5
©2008
1072 pages
INSTRUCTORS

STUDENTS


                               
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TITLE INFORMATION
Description  |  Author Info  |  New to This Edition  |  Hallmark Features  |  Sample Chapters  |  Reviewer Comments

                               
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Description
As with the first edition of CMOS: Circuit Design, Layout, and Simulation, the book provides an important contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much more. In this second edition, the authors have taken a new, two path approach to the topic. They develop design techniques for both long- and short-channel CMOS technologies and then compare the two. This approach results in explanations that are multi-dimensional and allows the reader deep insight into the design process. Complete with layout software for the PC, this exceptionally comprehensive presentation of CMOS integrated circuit design will guide you through the process of implementing a chip from the physical definition through the design and simulation of the finished chip. This revised edition will have have 100 new pages.  

                               
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[ 本帖最后由 benemale 于 2008-2-14 00:29 编辑 ]

SPICE.rar

1.38 MB, 下载次数: 176 , 下载积分: 资产 -2 信元, 下载支出 2 信元

SPICE Models

Cadence.part1.rar

2.52 MB, 下载次数: 146 , 下载积分: 资产 -2 信元, 下载支出 2 信元

Cadence Models

Cadence.part2.rar

2.37 MB, 下载次数: 140 , 下载积分: 资产 -2 信元, 下载支出 2 信元

Cadence Models

Electric.rar

396.09 KB, 下载次数: 116 , 下载积分: 资产 -2 信元, 下载支出 2 信元

Electric Models

Figures(PDF).part1.rar

4.3 MB, 下载次数: 94 , 下载积分: 资产 -3 信元, 下载支出 3 信元

Figures pdf

Figures(PDF).part2.rar

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Figures pdf

Figures(PDF).part3.rar

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Figures pdf

Problems.rar

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Additional Problems

Solutions.part1.rar

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Solutions Manual

Solutions.part2.rar

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Solutions Manual

Solutions.part3.rar

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Solutions Manual

Solutions.part4.rar

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Solutions Manual

BSIM4.3.0 MOSFET Model - User's Manual & CMOS_Model.txt.rar

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Table of Contents & Index 2nd Ed..rar

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 楼主| 发表于 2008-2-14 00:16:22 | 显示全部楼层

                               
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Larger Image
CMOS, Mixed-Signal Circuit Design
R. Jacob Baker
ISBN: 978-0-471-22754-0
Hardcover
520 pages
June 2002, Wiley-IEEE Press


Wiley List Price: US $88.95
This price is valid for China. Change location to view local pricing and availability.

How to Buy

Evaluation Copy
Instructors may request an evaluation copy for this title.


Read an Excerpt
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Chapter 30 - Data Converter Modeling
Chapter 31 - Data Converter SNR
Chapter 32 - Noise-Shaping Data Converters
Chapter 33 - Submicron CMOS Circuit Design
Chapter 34 - Implementing Data Converters
Chapter 35 - Integrator-Based CMOS Filters
Chapter 36 - At the Bench





An important continuation to CMOS: Circuit Design, Layout, and Simulation The power of mixed-signal circuit designs, and perhaps the reason they are replacing analog-only designs in the implementation of analog interfaces, comes from the marriage of analog circuits with digital signal processing. This book builds on the fundamental material in the author's previous book, CMOS: Circuit Design, Layout, and Simulation, to provide a solid textbook and reference for mixed-signal circuit design. The coverage is both practical and in-depth, integrating experimental, theoretical, and simulation examples to drive home the why and the how of doing mixed-signal circuit design. Some of the highlights of this book include:
  • A practical/theoretical approach to mixed-signal circuit design with an emphasis on oversampling techniques
  • An accessible and useful alternative to hard-to-digest technical papers without losing technical depth
  • Coverage of delta-sigma data converters, custom analog and digital filter design, design with submicron CMOS processes, and practical at-the-bench deadbug prototyping techniques
  • Hundreds of worked examples and questions covering all areas of mixed-signal circuit design


[ 本帖最后由 benemale 于 2008-2-14 00:26 编辑 ]

SPICE.rar

402.36 KB, 下载次数: 78 , 下载积分: 资产 -2 信元, 下载支出 2 信元

SPICE Models

Figures.rar

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Additional Problems & Solutions.part1.rar

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Additional Problems & Solutions.part2.rar

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 楼主| 发表于 2008-2-14 00:29:00 | 显示全部楼层

Errata for CMOS

Revised 2nd Edition,
ISBN-13:
978-0-470-22941-5, © 2008.

·
In the Revised 2nd Edition the software specific discussions, about 50 pages in chapters 1, 2, 3, and 5, were replaced with new material covering simulation and layout.
·
The Revised 2nd Edition is about 1 inch thinner than the earlier printings because a lower bulking paper is used.

Typos in the 3rd and later printings of the Revised 2nd Edition


·
page 979 - In Ex. 29.6 Vout should be = ¾ * Vref = 3.75V instead of ¼ * Vref = 1.25V

Typos fixed in the 2nd printing of the Revised 2nd Edition
·
page 18 – bottom of the page replace: - 0.294 with - 0.119, - 16.85 with - 6.82, and the time delay in Eq. (1.9), - 234 us with - 95 us
·
page 42 – second paragraph, second line “determining” is misspelled
·
page 53 – the triple-well figure should be 2.24d (not 2.24c), change in first paragraph “can be used, Fig. 2.24c.” to “can be used, Fig. 2.24d.”
·
page 54 – replace “Being able use the” with “Being able to use the”
·
page 61 – second line change “capacitance for metal1” to “capacitance for metal2”
·
page 77 – Fig. 3.23 should only have 6 pads on a side not 7 (so the total number of pads is 24 not 28)
·
page 686 – 14th line down change “and to eliminate the” to “and to eliminate, or more correctly to reduce, the”
·
page 687 – in Eq. (21.78) Av1 should be - gm1*ro/2. This means, in Ex. 21.12, that Av1 = - 3.75, tau_in = 1.16 ns, and thus fin = 137 MHz.


Typos fixed during the 2nd, 3rd, and 4th printings of the 2nd Edition (old edition), ISBN-13: 978-0-471-70055-5, published October 2004.
·
page 25 - swap vin and vout in Fig. 1.25 (vout < vin)
·
page 66 - the pulse delay in the SPICE netlist should be 50p not 5n
·
page 85 - Figure 4.2(f) subtitle should indicate (e) not (g)
·
page 86 - last line in second paragraph change "select" to "active"
·
page 88 - figure 4.4, there shouldn't be an oxide above the silicided MOSFET S/D
·
page 91 - there shouldn't be an oxide above the silicided MOSFET S/D in (h)
·
page 97 - in the ninth line from the bottom change "are" to "area"
·
page 99 - the rules show the minimum poly gate extension is 1 where it should be 1.25.
·
page 108 - Ex. 5.2 should be a 10k resistor not 50k
·
page 136 - two lines above Eq. (6.8) should be changed from "inversion and depletion cases." to "inversion and accumulation cases."
·
page 139 - Equation (6.17) the term Vfb should be Vfp
·
page 150 - a parentheses around nkT in Eq. 6.48
·
page 153 - indicate, in the last paragraph, that hot indicates carriers with higher than thermal equilibrium energy
·
page 174 - change the spinning direction of the wafer (not wrong just more common)
·
page 214 - capitalize Joules in four line
·
page 216 - modify figure 8.4 to show the power meter measures V^2,RMS and that the PSD is this power divided by the resolution of the spectrum analyzer
·
page 228 - second line, the word SPICE should be moved to above the figure
·
page 246 - ninth line down change 8.50 to 8.51
·
page 272 - third line down change series to parallel
·
page 273 - swap the + and - in Fig. 9.6b
·
page 275 - add 1 uA next to the current source in Fig. 9.9
·
page 284 - add t (time) to the bottom two equations (the sinusoids) on the page
·
page 285 - add a - in front of 0.5 mV third line down
·
page 289 - fix partially hidden VDS on the x-axis in Fig. 9.24
·
page 295 - indicate that the temperatures are in Kelvin for Eq. (9.52)
·
page 297 - indicate velocity overshoot and other effects cause the gm to increase with vgs
·
page 309 - problem 9.26 change the 9.1 to 9.2
·
page 311 - sixth line from the bottom change "is a 0 V" to "is at 0 V"
·
page 312 - change the direction of the pulse in Fig. 10.3b
·
page 327 - last line change "fetoprobes" to "femtoprobes"
·
page 341 - eighth line down change 11.13 to 11.15, above this change "Latch-Ip" to "Latch-Up"
·
page 348 - remove the 2 at the beginning of Eq. 11.28, and change comments describing RC line delay and the delay associated with the resistance driving the load C
·
page 376 - first line change Evaluating to Increasing
·
page 380 – Figure is spelled wrong in Figure 13.9
·
page 395 - first line change 13.5ps to 15.75 ps
·
page 446 - remove the word trench from the third line
·
page 447 - 9th line down change 8-Mbit to 16-Mbit
·
page 450 - 16th line down change "VDD is large" to "VDD is small", change the figure caption to 16.26 instead of 16.27
·
page 451 - 11th line from the bottom of the page change "power" to "current"
·
page 460 - last line change "(ideally) ,to" to "(ideally), to"
·
page 466 - fix the space after the word higher in Fig. 16.53
·
page 468 - change the direction of electron flow in Fig. 16.56
·
page 471 - capitalize NAND in the figure caption of Fig. 16.61
·
page 488 - fourth line from the bottom change "constant ,we" to "constant, we"
·
page 495 - fourth line from the bottom should be 17.11b not 17.11a
·
page 500 - first line change 17.15 to 17.16
·
page 513 - Eq. 17.42 the (N - M)/M should be M/(N - M) also change N/2<=M<=N to 0<=M<=N/2
·
page 517 – second paragraph from bottom change “The thermal noise from the capacitors is” to “The input-referred thermal noise is set by the sampling capacitors and is…”
·
page 518 - Fig. 17.38 flip the polarity of the offset and first line of second paragraph change 17.33 to 17.36
·
page 545 - second to the last line should be (N+1)*VDD - N*VTHN and N*VDD - N*VTHN
·
page 546 - fourth line from the bottom in first paragraph change "A larger capacitor is used on node A" to "A larger capacitor is used on node B"
·
page 553 - fourth line down capabilities is spelled wrong
·
page 554 - seventh line down add an s to continue
·
page 564 - fifth line up change 1 mV to 10 mV
·
page 604 - first line change 10k to 5k
·
page 618 - problem 19.14 change "that it" to "that it is"
·
page 615 - fig. 20.4 change the 210k resistor to 200k
·
page 620 - tenth line down change 0.2 to 0.1
·
page 625 – write Eq. (20.23) in terms of the overdrive voltage as well (IREF=
and Vov=)

·
page 637 - second line from the bottom change "drain" to "drain voltage" also change the MOSFET references to they refer to the correct MOSFETs
·
page 639 - Fig. 20.31b change the VGS on the gate of M4 to simply VG
·
page 649 - Fig. 20.45b fix typo of MB7 to MB6 (second row of PMOS)
·
page 651 - fourth line down change Vbias2 to Vbias4
·
page 657 - eighth line from bottom fix space in "common- source". In the last line change from 21.1 to 21.1a
·
page 667 - remove square-root brackets in Eq. (21.21)
·
page 674 - first line of second paragraph add extra parentheses so they are balanced
·
page 686 – Eq. (21.75) should be “V^2inoise =…” instead of “V^2onoise =…”
·
page 687 - take the magnitude of the second to the bottom equation
·
page 688-690 - equations (21.84) and (21.85) are only valid when the drain of M2 is connected to a low impedance. Also, remove noise from M2/M3 in Eqs. (21.79) and (21.80) See here for updated pages.
·
page 692 - second line from the bottom change 600 mV to 500 mV, last paragraph change all 250 mV to 280 mV
·
page 694 – remove M2’s noise contributions in Eq. (21.99), show why in Fig. 21.44
·
page 697 – replace the W in Eq. (21.108) with K and indicate K=12.5 (the gm scales linearly with the MOSFET’s width) and change 530 uA/V to 1.875 mA/v. Change, in the next equation, 1.88k to 533 and 0.84 to 0.95, two lines below that change 500*0.84 = 420 ==> 52.5 dB to 500*0.95 = 425 ==> 53 dB
·
pages 697-703 - The symbols RL and Rload are used interchangeably. Should, to be consistent, just use Rload.
·
page 702 – first equation, move the 1k out of the brackets for a Pload of 125uW, the Psupply becomes 325uW, the PCE becomes 38%, without bias circuit current PCE is 68%
·
Page 715 – 11th
line from the bottom change “folded- cascode” to “folded-cascode”

·
page 717 - fix the formatting of the Iss in Eq. 22.15
·
page 718 - Ex. 22.4 add an s to components, remove the s on drains, add the word current after drain, and change 150 uA/V^2 to simply 150 uA/V
·
page 719 - change, in Fig. 22.10's caption, 22.10 to 22.4, two lines above Eq. (22.20) change “the AC current flowing in ro4 is id1.” to “the AC current flowing in M4 is id1.” (change ro4 to M4)
·
page 726 - eq. (22.32) the output noise is divided by A^2d (not the input noise), change the label on the noise source for M3 in Fig. 22.20 from 6 to 3
·
page 735 - should be 3.6 V not 3.65 V and 4.4 V not 4.45 V in Ex. 22.9
·
page 746 - fourth line down should indicate Ch. 5 not Ch. 7
·
page 749 - remove VSS from Eq. (23.8)
·
page 762 - Ex. 23.4 should say using Eq. (23.23) not (23.22)
·
page 765 – add a start-up circuit to Fig. 23.27
·
page 766 - change the simulation and discussion to include the start-up circuit added on the previous page
·
page 769 - change figs. 23.31 and 32 as seen at: http://cmosedu.com/cmos1/book.htm
·
page 774 – fifth and seventh lines from the bottom change 900 mV to 930 mV
·
page 785 - indicate equation (24.19) is an approximation for |K*Cc/gm1| >> Cc/gmcg
·
page 790 - Eq. 24.27 should have Acm not Ac
·
page 791 - fourth and first lines from the bottom change 20.21, 21.21 to 23.21
·
page 792 - Eq. (24.31) should indicate open loop gain AOL not just A
·
page 793 - last line remove the square-root bracket can change the gain to -31.6
·
page 794 - first line change gain from 5,000 to 15,600 and gain from 74 dB to 84 dB, also remove square-root in fourth line down
·
page 795 - first line remove the word "and"
·
page 800 - last line in second paragraph change fig. 24.38 to fig. 24.39
·
page 802 - fig. 24.40 shift vm down a little
·
page 817 - after equation (24.76) should say CLmin not CLmax
·
page 820 - fourth line in second paragraph fix space in "common- source"
·
page 822 - fourth line from the bottom should be 2400 fF not 2400 pF
·
page 851 - fix caption for Fig. 25.29a
·
page 873 - change caption for Fig. 26.14
·
page 880 - second line from the bottom fix space in "common- mode"
·
page 897/898 - change 10f to 50f and the 25f to 10f in Fig. 26.50 (not wrong just a little more robust)
·
page 908 - change the word edition to volume in problem 26.19
·
page 919 - fix space in "cross- coupled" sixth line from top, fix fig. 27.16 caption
·
page 950 - third line from the bottom change 011 to 100
·
page 1018 - problem 29.6 change "Fig. P29.6" to "Fig. 29.52"
·
page 1019 - problem 29.7 change "5 mA" to "5 uA"
·
augmented index in second and later printings

发表于 2008-2-14 09:22:23 | 显示全部楼层
借鉴!谢谢
发表于 2008-2-14 09:28:54 | 显示全部楼层
有Ebook??
 楼主| 发表于 2008-2-14 09:36:09 | 显示全部楼层


原帖由 semico_ljj 于 2008-2-14 09:28 发表
有Ebook??



跟大家一样,只有bonyou发的扫描版和第二本书的中文版,没有文字版。。。
发表于 2008-2-24 19:35:43 | 显示全部楼层
可惜没有书啊
 楼主| 发表于 2008-2-24 22:26:17 | 显示全部楼层
论坛里有这本书啊,不过是扫描版的。。。
发表于 2008-3-3 09:52:15 | 显示全部楼层

有用吗?

下载试试看。
发表于 2008-3-3 09:58:56 | 显示全部楼层

都全吗?

都全吗
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