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SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters
Although very high update rates are achieved in recent publications on high resolution D/A converters, the bottleneck in the design is to achieve a high spurious free output signal bandwidth. The influence of the dynamic output impedance on the chip performance has been analyzed and has been identified as an important limitation for the spurious free dynamic range (SFDR) of high resolution DAC's. Based on the presented analysis an optimized topology is proposed
Published in:Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on (Volume:3 ) Date of Conference:1999 Page(s):1193 - 1196 vol.3 Meeting Date :05 Sep 1999-08 Sep 1999 Print ISBN:0-7803-5682-9 INSPEC Accession Number:6558683 Conference Location  afos DOI:10.1109/ICECS.1999.814383 Publisher:IEEE
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发表于 2014-8-6 10:26:50
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