AMD 北京site内推 DV engineer

xiaoyao0209

AMD Beijing DFx team 招聘！！！
简历发至：550255434@163.com
勿站内

Position:  ASIC/ Layout Design Engineer-DV

Job Description:  
  
Qualified candidate will perform some or all functions below:

1.    Participate in SOC full Chip DFT feature and architecture definition
2.    Responsible for DFT specification generation and review
3.    Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4.    Perform verification on all DFT structures
5.    Generate DFT related timing constraints and work with PD team for timing closure
6.    Generate and verify DFT structural patterns and functional patterns
7.    Participate in ATE bring-up and debug the DFT patterns on ATE
8.    Design and implement other DFX (debug, characterization, yield etc) logics
                                                         

Requirements/Qualifications:


-   BS in EE & CS.  MS preferred, with 0-3 years experience.
-   Hands on working experience on ASIC DFT design and verification
-   Familiar with entire ASIC design flow
-   Experience with micro processor design a big plus
-   Should have strong problem solving skills
-   Good English hearing, speaking, reading and writing capabilities
-   Good communication skills

xiaoyao0209

欢迎踊跃投简历

cheernixue

又是猎头消息，官网有吗？

xiaoyao0209

额，从哪看出是猎头？，我是货真价实的AMD员工哦，:victory ，这个是新open出来的职位，官网上还没挂出来，欢迎大家踊跃投简历哈

飞扬紫百合

回复 1# xiaoyao0209


    我看怎么是做DFT的？有验证的职位么？