想问一下，怎么统计电路中每个节点为0或1的概率

zuiqiangzhe

有待测电路，我需要给这些电路随机输入激励N次，然后统计每个节点（内部节点和输出）的次数，大致算出每个节点的概率。
该怎么搭平台呢？tetramax、perl。
望大家教教。

icfbicfb

有输出文本么，perl可以的

sjtusonic

回复 1# zuiqiangzhe


    记得描述翻转率的有种通用文件叫saif，你看看你的EDA软件能不能写出saif。
这样就省得你自己写脚本了

zuiqiangzhe

回复 2# icfbicfb


    你好，想问下，怎么统计内部节点为0和1的概率呢？

zuiqiangzhe

回复 3# sjtusonic


    你好，能说详细些吗？

sjtusonic

Parallel SAIF
SAIF is Switching Activity Interchange Format, a file format for
Power Compiler. VCS writes or dumps SAIF files for it.
Parallel SAIF is a feature to improve runtime performance. Parallel
SAIF uses the VCS Multicore Application Level Parallelism (ALP)
capability for multicore machines. In it Parallel SAIF uses a
consumer or slave process to write or dump SAIF files while the
simulation is run by the producer or master process.
Serial SAIF dumping, that is having VCS write SAIF files without
using the advantage of a multiple processor machine, is of course
still supported.
You specify Parallel SAIF with the -parallel+saif compile-time
or runtime option.

Introduction to SAIF Files
The accuracy of the power calculations used by Power Compiler depends on the accuracy of the switching activity. Switching activity is calculated using RTL or gate-level simulation and is stored in a SAIF file. You can use the SAIF file to annotate switching activity information on the design objects before you perform power optimization and analysis.

SAIF is an ASCII format supported by Synopsys to facilitate the interchange of information between various Synopsys tools. You use the read_saif command to read SAIF file and the write_saif command to write out the SAIF file. For more information, see the man pages.

Converting a VCD file to a SAIF File
The vcd2saif utility converts the RTL or gate-level VCD file generated by VCS into a SAIF file. This utility has limited capability when the VCD is generated from the SystemVerilog simulation as described in “Limited SystemVerilog Support in vcd2saif Utility”.

The vcd2saif utility is architecture-specific and is located in install_dir/$ARCH/syn/bin. The $ARCH environment variable represents the specific platform (architecture) of your Synopsys software installation, such as linux, AMD.

You can use compressed VCD files (.Z) and gzipped VCD files (.gz). In addition, for VPD files, you can use the utility located at $VCS_HOME/bin/vpd2vcd, and for FSDB files, you can use the utility located at $SYNOPSYS/bin/fsdb2vcd.

You can use the following syntax for the vcd2saif utility for RTL simulation and gate-level simulation:

vcd2saif -instance_path vcd_file -output bsaif
vcd2saif
    [-instance path ...]
    [-format lang] [-testbench lang]
    [-verilog_instance path] [-vhdl_instance path]
    [-no_div] [-keep_leading_backslash] [-time]

The vcd2saif utility does not support state-dependent and path-dependent switching activity. For information about each option, use the vcd2saif -help command.

以上只是关于saif的相关信息，不知与你的使用要求是否吻合。

zuiqiangzhe

回复 6# sjtusonic


    谢谢了，我先看看

新嘴小王安子

请问你这个问题解决了吗，现在遇到和你一样的问题的，求解答，O(∩_∩)O谢谢