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synopsys "cocentric" system studio

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发表于 2012-5-12 00:20:44 | 显示全部楼层 |阅读模式

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i think that the synopsys "cocentric" system studio is best tool for system design.
it's like simulink but it use based of systemc and c for simulation.

can anybody share it?
 楼主| 发表于 2012-5-12 01:27:13 | 显示全部楼层
datasheet here
http://oron.com/ky6raxa22rpr
发表于 2012-5-12 06:24:42 | 显示全部楼层
本帖最后由 ald_syn_cad 于 2012-5-12 06:27 编辑

Hi speakeet1!

I have tested lots of tools for system designing specially considering DSP applications like ADS, SystemVue, Xilinx System sudio and... but this is something else although ADS has more models and also analytic simulation capabilities.

I think among the EDA giants (Mentor, Cadences, Synopsys) this soft has the most complete features for integrating pre-built modes and other languages (including RTL and algorithmic C++ ones) and also code generation and these are its major differences.

By the way this is primary for simulation and its created codes can not be easily design entry to the HLS tools and need lots of modifications.

As I said these kinds of tools are only good for DSP applications (perfect for data flow) and can only model the behavior of the undelaying system not true hardware descriptions.

You can not model interactions of blocks with each other easily (like TLM2 do that) and also processors model can not be entered to your design flows.

If they could do these jobs no architectural design tools were emerged (like Mentor vista, Cadence System Development Suite or Synopsys Platform architect).

As I said your introduced soft is only for integrating simulation models although it provides integrating with HDL simulators. I have choosen the below sentence from your posted data sheet:

"Matlab, HDL and SystemC models can be easily imported and co-simulated, an algorithm design of any complexity can be exported as C++ or SystemC models, for integration into any C/C++ or SystemC-enabled verification flow."

In datasheet it has said that dataflow and control but control is only for syncing the blocks not truly controling your system from hardware perspective. Lots of its used models (I can say near 90%) are not simply synthesizable.

After all this soft is unique and really simplifies your DSP designs and simulations by stepping through mid hardware arena.

If anyone could upload this, I'd be so thankful!
发表于 2012-5-12 23:23:51 | 显示全部楼层
没看到有人分享
发表于 2012-5-13 00:24:26 | 显示全部楼层
本帖最后由 ald_syn_cad 于 2012-5-13 00:27 编辑

See its available pre-built models and compare with ADS and SystemVue
All_models.jpg
发表于 2012-5-13 07:37:56 | 显示全部楼层
From Vietnamese forum:
"Can you please please please help me (english help) on installing IC Compiler 2010 That are posted in this topic. I am almost newbie in linux but I am using EDA for about 8 years. My university MS thesis is "Hardware implementation of turbo code" and I really nead a physical compiler.I have search web and found that IC Compiler is an ideal tool for this reason."
From kindergarten "Sonsivri":
" I think it's better to focus on CatapultC (It is the best in the market and all of competitors are trying to mimic its capabilities) and after learning c/c++ or SystemC (maybe after 5 years) you would have better knowledge of choosing appropriate tools for your tasks. By the way if you have not started learning c++ (because the real power of CatapultC is shown when using template and classes that are in c++ not c) it's better to use the following book. By learning that book (it is for software designers not hardware ones but learning structures, I mean templates, classes of c++ is so easy) you can understand almost the important reason of defining include files that are the foundation of CatapultC.
book:
BEGINNING VISUAL C++® 2010
-----------------------------------------------------------------
First install vmware 8 and redhat enterprise 6 with all components. If you have problem installing them tell me start from beginning."
"This is my Turbo decoder project. It's results are surprisingly true. It can be fully synthesizable to Virtex family up to 350 MHZ. Currently I am trying to reduce memory and control logic requirements. It's throughput is 30000 clock cycle for 8 iterations......"
"Wow, thats impressive, what is the turbo decoder used for? What design constraints are you under?"
"Nevertheless, despite all the difficulties I am ready and motivated to experience IC design tools. Dear Aldec_forever, I find (by reading this forum) that you are experienced IC designer. I wold like to feel free to ask you for some advices.
I have downloaded Synopsis tools you have posted in the forum (100x thank you for this!) together with licensing tool and I will certainly try to install it and make it working. There is another question bothering me...up to you which version of Linux OS to choose because I could conclude that this is another issue in forum discussions? Is it OK to use Virtual Mashine (VMware) for emulating the Linux ? Do you have some Cadence installation, together with licensing tutorial and some e-books for the starting point (Cadence, Synopsis, Linux tutorials, IC design flow books etc) ? Do you prefer Synopsis or Cadence tools ?
Please help me to find the path in this crossroads of my life way."
Here:
"I have tested lots of tools for system designing specially considering DSP applications like ADS, SystemVue, Xilinx System sudio and... but this is something else although ADS has more models and also analytic simulation capabilities.

I think among the EDA giants (Mentor, Cadences, Synopsys) this soft has the most complete features for integrating pre-built modes and other languages (including RTL and algorithmic C++ ones) and also code generation and these are its major differences. .................."
"See its available pre-built models and compare with ADS and SystemVue ...."

INTERESTING
NOT BAD SOURCE CODE!
发表于 2012-5-15 20:07:43 | 显示全部楼层
求cocentric system studio破解icense
发表于 2012-5-15 20:07:45 | 显示全部楼层
求cocentric system studio破解icense
发表于 2012-5-15 20:08:44 | 显示全部楼层
我是搞ESL的,没有用过ADS,谁能提供ADS试用一下。多谢!
发表于 2012-5-15 20:08:45 | 显示全部楼层
我是搞ESL的,没有用过ADS,谁能提供ADS试用一下。多谢!
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