|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
职位描述如下：
The ideal candidate will have a Master’s degree, along with a theoretical background and practical experience of 2 years or more in the mixed-signal IC design industry. Competency in digital design, system implementation, and understanding fundamental digital circuits including finite state machines, synchronous/asynchronous de-bounce and de-glitch circuitry, clock and reset strategies, binary/gray code encoding, and serial communication interfaces (I2C/SPI) is necessary.
This engineer must be capable of RTL design using Verilog/VHDL, verification using automatic checking testbenches, code coverage analysis, synthesis, scan insertion, place and route, logical equivalence checking, static timing analysis, and interfacing with Cadence analog tools such as Virtuoso.
This engineer must possess good communication (written, spoken, listening) skills and the ability to work in a cross-functional team to develop world class mixed-signal ICs. The ability to accurately and clearly communicate capabilities and results to customers is also required.
Other responsibilities include:
• In the planning phase, this engineer must be able to quickly understand functionality of existing circuit solutions and identify/propose unique, high value solutions.
• Understanding IC fabrication processes and digital library deliverables and translating process capabilities and system level requirements into real world designs.
• Quickly generating prototype simulation models and testbenches for quick feasibility analysis
• Designing a comprehensive verification infrastructure for thorough analysis of RTL design
• Understanding of synthesis steps and ability to debug RTL implementations that are not compatible with synthesis
• Understanding of scan synthesis and proper digital scan circuit implementations
• Implementation of floorplan, power plan, clock tree structures
• Static timing analysis, constraint refinement, and timing closure
• Logical equivalence checking
• Creating schematic and layout databases compatible with the analog design tools (Cadence Virtuoso)
• Proficient use of oscilloscopes, arbitrary waveform generators, and measurement devices for laboratory evaluation of new silicon and competitive analysis
简历接收邮箱:
ti_recruiter@hotmail.com |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2012-3-21 17:37:24
楼主
