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本帖最后由 wisewater 于 2011-8-10 15:23 编辑
内部推荐，有意者请发简历到wisewater@163.com Title: Senior Design VerificationEngineer for Image Signal Processor Role and Chance l Understand functionalities of design in architecture and design specifications. Write the functional validation part of test plan from block level to SoC level to achievethe functional coverage requirements. l Deliver bug-free C-model from algorithm level to cycle level. l Be responsible for test case composition, testbench and test environment setup,test automation tool development, BFM model coding and debugging. l Support testing for DFP, DFT and FPGA l Apply necessary verification methodologies to ASIC design, such as coverage, assertion,randomization, gatesim etc and achieve the verification goals l Support FW/SW bring-up and debugging l Working as the technical point of contact on the ASIC area. Responsibilities: 1. Major in CS or EE and have Master degree or higher 2. 3 years beyond working experience on ASIC designverification 3. Must have strong background on image processing algorithms 4. Must be proficient in C++ programming and debugging inLinux and Windows platforms. Know well about SW engineering. 5. Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools. 8. Must be skillful in shell/perl/tcl/Makefile programmingin linux OS. 9. Should have adequate ASIC design knowledge and be able todebug RTL codes using corresponding tools 10. Good English hearing, speaking, reading and writingcapabilities. 11. Will be a big plus if having tape-out experience. | 
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发表于 2011-8-10 15:05:58
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