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Contributor: swamiv
Date: March 28, 2011
Description: The UVM Reference Flow version 1.02 has been updated to align with the Accellera uvm-1.0 release (uvm-1.0p1). It applies the Universal Verification Methodology (UVM) to a Block and Cluster Verification in a SoC Design. The UVM Reference Flow was developed by Cadence to show the best practices for applying UVM to the verification of a block, a Universal Asynchronous Receiver Transmitter (UART). It then shows how to reuse the block level verification environment when verifying a cluster design (an APB subsystem) into which the UART is integrated along with other design components (viz. SPI, GPIO, Power Controller, Timers etc…). |
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