2000年JSSC论文合集

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在《2010年（1-11月）JSSC论文合集》一文中，我上传了2010年的JSSC论文合集，大家反响不错，都很支持我，以后我会持续更新，望大家多多关注^_^。
下面是2000年（1-6月）JSSC论文合集。按每期（一月一期）分类发布，每期的内容列表放在压缩包前面，方便大家查阅。

PS:《2010年（1-11月）JSSC论文合集》如下：
      http://bbs.eetop.cn/viewthread.php?tid=273242

Issue 1

1.Analog ALC Crystal Oscillators for High-Temperature Applications
2.Noise in RF-CMOS Mixers：A Simple Physical Model
3.Active Capacitor Multiplier in Miller-Compensated Circuits
4.1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology
5.A Stereo Audio Chip Using Approximate Processing for Decimation and Interpolation Filters
6.A CMOS Analog Timing Recovery Circuit for PRML Detectors
7.A Multigigahertz Josephson–Semiconductor Interface Circuit Using 77-K Differential Monolithic HEMT Amplifier      and 4.2-K JJ High-Voltage Driver for Superconductor-Semiconductor
8.A Multi-Level Multi-Phase Charge-Recycling Method for Low-Power AMLCD Column Drivers
9.CMOS Stress Sensors on (100) Silicon
10.Phase Noise Degradation at High Oscillation Amplitudes in LC-Tuned VCO’s
11.A Packaged 1.1-GHz CMOS VCO with Phase Noise of -126 dBc/Hz at a 600-kHz Offset
12.A 71-MHz CMOS IF-Baseband Strip for GSM
13.CMOS Switched-Op-Amp-Based Sample-and-Hold Circuit
14.Single-Ended SRAM with High Test Coverage and Short Test Time
15.Low-Power Embedded SRAM with the Current-Mode Write Technique
16.A Scannable Pulse-to-Static Conversion Register Array for Self-Timed Circuits
17.Corrections to“A High-Swing CMOS Telescopic Operational Amplifier”
Issue 1.rar (2.65 MB , 下载次数: 193 )

2010-12-7 19:35 上传

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Issue 2

1.Pulsewidth control loop in high-speed CMOS clock buffers
2.Optimized test circuits for SER characterization of a manufacturing process
3.A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
4.Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions
5.Speed and power scaling of SRAM's
6.MOS transistor modeling for RF IC design
7.An analog beam-forming circuit for ultrasound imaging using switched-current delay lines
8.CMOS high-frequency switched-capacitor filters for telecommunication applications
9.Three-stage large capacitive load amplifier with damping-factor-control frequency compensation
10.A fully integrated 0.5-5.5 GHz CMOS distributed amplifier
11.A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line
12.A CMOS delta-sigma true RMS converter
13.A distributed selector IC using GaAs MESFET's with multilayer-interconnection structure
14.A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection
15.A double-sampling pseudo-two-path bandpass ΔΣ modulator
16.A pipeline AD converter architecture with low DNL
17.Comments on “Design issues in CMOS differential LC oscillators” [and reply]
Issue 2.rar (3.14 MB , 下载次数: 195 )

2010-12-7 19:40 上传

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Issue 3

1.A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR
2.An 8-bit 150-MHz CMOS AD converter
3.A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC
4.Oscillator phase noise：a tutorial
5.Design of high-Q varactors for low-power wireless applications using a standard CMOS process
6.Bandwidth extension in CMOS with optimized on-chip inductors
7.A 1.3 GHz low-phase noise fully tunable CMOS LC VCO
8.A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbi detector for disk drive read channels
9.A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications
10.An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter      performance
11.Low-power direct digital frequency synthesis for wireless communications
12.A highly versatile beamforming ASIC for application in broad-band fixed wireless access systems
13.A single-chip narrow-band frequency-domain excisor for a Global Positioning System (GPS) receiver
14.A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP
15.Bus architecture of a system on a chip with user-configurable system logic
16.Watermarking-based copyright protection of sequential functions
17.Mixed-signal quadrature demodulator with a multicarrier regeneration system
18.An analog record, playback, and processing system on a chip for mobile communications devices
19.A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications
20.Guest editorial
Issue 3.part1.rar (4.77 MB , 下载次数: 2157 )

2010-12-7 19:44 上传

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Issue 3.part2.rar (1.04 MB , 下载次数: 225 )

2010-12-7 19:45 上传

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Issue 4

1.A 16-bit 250-kHz delta-sigma modulator and decimation filter
2.A 1.8-mW CMOS ΣΔ modulator with integrated mixer for AD conversion of IF signals
3.A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver
4.An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
5.Widely programmable high-frequency continuous-time filters in digital CMOS technology
6.High-Q HF microelectromechanical filters
7.A CMOS uncooled heat-balancing infrared imager
8.A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing
9.A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor
10.Advanced controlling scheme for a DRAM voltage generator system
11.Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz
12.An ultra low power adaptive wavelet video encoder with integrated memory
13.Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops
14.A 10-Gbps high-isolation, 16×16 crosspoint switch implemented with AlGaAs-GaAs HBT's
15.Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process
16.A simple subcircuit extension of the BSIM3v3 model for CMOS RF design
17.Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits
18.1.2-V CMOS op-amp with a dynamically biased output stage
19.Digitally programmable switched-current FIR filter for low-voltage applications
20.A 1-V, 8-bit successive approximation ADC in standard CMOS process
21.A 1-V 6-b 50-MSps current-interpolating CMOS ADC
22.Low-power CMOS digital design with dual embedded adaptive power supplies
23.A low logic depth complex multiplier using distributed arithmetic
24.A robust, load-insensitive pad driver
Issue 4.part1.rar (4.77 MB , 下载次数: 255 )

2010-12-7 19:48 上传

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Issue 4.part2.rar (3.91 MB , 下载次数: 171 )

2010-12-7 19:50 上传

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Issue 5

1.A source-line programming scheme for low-voltage operation NAND flash memories
2.A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming
3.A robust 8F2 ferroelectric RAM cell with depletion device (DeFeRAM)
4.A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read_write-back scheme
5.Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus
6.A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
7.Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps
8.A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors
9.100000-pixel, 120-dB imager in TFA technology
10.A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
11.A 3.6-Gbps 340-mW 16：1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology
12.A 0.3-μm CMOS 8-Gbps 4-PAM serial link transceiver
13.A 5-GHz CMOS wireless LAN receiver front end
14.A wide tuning range gated varactor
15.A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver
16.A 2.6GHz-5.2GHz frequency synthesizer in 0.4-μm CMOS technology
Issue 5.part1.rar (4.77 MB , 下载次数: 191 )

2010-12-7 19:53 上传

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Issue 5.part2.rar (1.69 MB , 下载次数: 169 )

2010-12-7 19:53 上传

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Issue 6

1.A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications
2.A low-noise phase-locked loop design by loop bandwidth optimization
3.A CMOS two-path tree search detector
4.A 2-Mbps 256-state 10-mW rate-1-3 Viterbi decoder
5.An architecture of high-performance frequency and phase synthesis
6.Differential CMOS circuits for 622-MHz_933-MHz clock and data recovery applications
7.An all-digital low-power IF GPS synchronizer
8.nMOS reversible energy recovery logic for ultra-low-energy applications
9.Improved sense-amplifier-based flip-flop：design and measurements
10.A 2-GHz clocked AlGaAs_GaAs HBT byte-slice datapath chip
11.A scalable substrate noise coupling model for design of mixed-signal IC's
12.On the use of MOS varactors in RF VCOs
13.A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives
14.A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission
15.Comments on “New dynamic flip-flops for high-speed dual-modulus prescaler”
16.Correction to “CMOS high-frequency switched-capacitor filters for telecommunication applications”
17.Correction to “a fully integrated 0.5-5.5-GHz CMOS distributed amplifier”
Issue 6.part1.rar (4.77 MB , 下载次数: 263 )

2010-12-7 19:55 上传

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Issue 6.part2.rar (312.47 KB , 下载次数: 138 )

2010-12-7 19:38 上传

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tiger2031573

xiexie

liude19832006

楼主怎么不上传了，你不是有十年的论文吗

ivyjue

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ivyjue

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ivyjue

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ivyjue

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ivyjue

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ivyjue

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ivyjue

thanks