JSSC 2010 December 12月: 13 files

angelweishan

13 files

New Associate Editors

U Moon 2503

Introduction to the Special Issue on the 2010 IEEE International Solid-State Circuits Conference

G-H Cho, B Murmann, K Halonen, R Gharpurey, and J-Y Sim 2505

A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS With an Absolute Inaccuracy of 01% From -55 C to 125 C

S M Kashmiri, M A P Pertijs, and K A A Makinwa 2510

A Micropower Chopper—CDS Operational Amplifier
M Belloni, E Bonizzoni, A Fornasari, and F Maloberti 2521

A Class-G Headphone Amplifier in 65 nm CMOS Technology
A Lollio, G Bollati, and R Castello 2530

A Two-Phase Switching Hybrid Supply Modulator for RF Power Amplifiers With 9% Efficiency Improvement
P Y Wu and P K T Mok 2543

A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS
Y K Ramadass, A A Fayed, and A P Chandrakasan 2557

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator
M H Perrott, S Pamarti, E G Hoffman, F S Lee, S Mukherjee, C Lee, V Tsinker, S Perumal, B T Soto, N Arumugam, and B W Garlepp 2566

A 21-to-28-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

T Tokairin, M Okada, M Kitsunezuka, T Maeda, and M Fukaishi 2582

A 12-V 10- W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 02 C (3 ) From -70 C to 125 C
F Sebastiano, L J Breems, K A A Makinwa, S Drago, D M W Leenaerts, and B Nauta 2591

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration
A M A Ali, A Morgan, C Dillon, G Patterson, S Puckett, P Bhoraskar, H Dinc, M Hensley, R Stop, S Bardsley, D Lattimore, J Bray, C Speir, and R Sneed 2602

A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR
R Payne, M Corsi, D Smith, T-L Hsieh, and S Kaylor 2613

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp
B Hershberg, S Weaver, and U Moon 2623

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC
G Taylor and I Galton 2634

An 18 b 125 MS/s ADC With 93 dB SNR
C P Hurrell, C Lyden, D Laing, D Hummerston, and M Vickery 2647

A Millimeter-Wave Intra-Connect Solution
K Kawasaki, Y Akiyama, K Komori, M Uno, H Takeuchi, T Itagaki, Y Hino, Y Kawasaki, K Ito, and A Hajimiri 2655

A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging
A Arbabian, S Callender, S Kang, B Afshar, J-C Chien, and A M Niknejad 2667

A 60-GHz Band 2 2 Phased-Array Transmitter in 65-nm CMOS
W L Chan and J R Long 2682

A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface
C Andrews and A C Molnar 2696

A CMOS Broadband Power Amplifier With a Transformer-Based High-Order Output Matching Network
H Wang, C Sideris, and A Hajimiri 2709

A 35 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation
E Temporiti, C Weltin-Wu, D Baldi, M Cusmai, and F Svelto 2723

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning
L Fanori, A Liscidini, and R Castello 2737

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
J Lee, Y-A Li, M-H Hung, and S-J Huang 2746

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications
A Valdes-Garcia, S T Nicolson, J-W Lai, A Natarajan, P-Y Chen, S K Reynolds, J-H C Zhan, D G Kam, D Liu, and B Floyd 2757

A Fully Integrated 2 1 Dual-Band Direct-Conversion Mobile WiMAX TransceiverWith Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS
J Deguchi, D Miyashita, Y Ogasawara, G Takemura, M Iwanaga, K Sami, R Ito, J Wadatsumi, Y Tsuda, S Oda, S Kawaguchi, N Itoh, and M Hamada 2774

A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization
H Ishihara, M Hosoya, S Otaka, and O Watanabe 2785

A 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform
M Ingels, V Giannini, J Borremans, G Mandal, B Debaillie, P Van Wesemael, T Sano, T Yamamoto, D Hauspie, J Van Driessche, and J Craninckx 2794

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS
K Koli, S Kallioinen, J Jussila, P Sivonen, and A Pärssinen 2807

A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC
M S-W Chen, D Su, and S Mehta 2819

A 47 10 Gb/s 14 mW/Gb/s Parallel Interface in 45 nm CMOS
F O’Mahony, J E Jaussi, J Kennedy, G Balamurugan, M Mansuri, C Roberts, S Shekhar, R Mooney, and B Casper 2828

A 123-mW 125-Gb/s Complete Transceiver in 65-nm CMOS Process
K Fukuda, H Yamashita, G Ono, R Nemoto, E Suzuki, N Masuda, T Takemoto, F Yuki, and T Saito 2838

A 45 mW/Gb/s 64 Gb/s 22+1-Lane Source Synchronous Receiver CoreWith Optional Cleanup PLL in 65 nm CMOS
R Reutemann, M Ruegg, F Keyser, J Bergkvist, D Dreps, T Toifl, and M Schmatz 2850

An 85-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer
D Lee, J Han, G Han, and S M Park 2861

A 1 GHz ADPLL With a 125 ps Minimum-Resolution Sub-Exponent TDC in 018 m CMOS
S-K Lee, Y-H Seo, H-J Park, and J-Y Sim 2874

mtwumtwu

so m,any useful materil, TKS for sahring

fsgbeyond

good ^^^^^^

frozenduck

thanks

frozenduck

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frozenduck

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frozenduck

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frozenduck

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frozenduck

thanks