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查看: 4404|回复: 7

[招聘] 内部推荐marvell IC设计、验证工程师

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发表于 2010-9-15 18:19:49 | 显示全部楼层 |阅读模式

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发简历至fanfantasy2004@163.com

ASIC Design
position 1:
DescriptionResponsible for digital audio system design and advanced algorithm development, such as echo-cancel
and noise reduction. Responsible for implementation of such system through ASIC designs. Needs to
work on the bench for chip debugging and testing.

QualificationsMinimum Requirements:
Undergraduate or graduate studies with micro-electronics background and basic knowledge about
mixed-signal integrated circuit design.
Experienced with ASIC design flow
Experienced with audio sytem design and algorithm development
Experienced with audio test procedure and common standards
Familiar with Unix and Windows operating system for script writing or post-processing.
position 2:
Derived from historic Data Storage and Datacom IC R&D, the IC R&D – Shanghai develop and implement advanced digital signal processing technologies and integrate advanced mixed-signal technologies for Storage Read Channel, Gigabit Ethernet, SATA PHY, Digital TV and other products. The digital design group is dynamic, exciting and rewarding, with many opportunities for professional growth for a motivated candidate.

You enjoy to follow through from circuit architecture conception to circuit implementation and verification, and to master the challenges of advanced deep sub-micron process technologies. You will also work on pure ASIC flow or full custom ASIC design flow to achieve high speed clock requirement of Giga Hz level and low power design target. You work closely with your peers, system architects, application engineers, field application engineers, and product engineers to find the optimal and most cost efficient solution for our customers. We provide ample opportunity to put your creativity to test.

Description:
* Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines using state-of-the-art IC design methodologies and design flows.
* Design high-speed data paths to implement arithmetic functions and signal processing algorithms.
* Write RTL code for high-speed and multi-clock domain designs.
* Perform functional verification of designs on block and chip level.
* Perform synthesis and pre- and post-layout timing closure.
* Oversee and guide layout and physical verification activities.
* Contribute test specifications and support evaluation of the design in coordination with application and product engineering.
* Provide design documentation, descriptions and information to application engineers, field application engineers, product engineers, and customers.

Qualifications:

* Master in Electronic, Communications, Microelectronics Engineering and Computer Science.
* 1 year of experience in digital design, with coding, simulation, verification, synthesis, or STA
* Understanding the basic Analog/digital circuit building blocks.
* Able to use spice, verilog and layout tools for circuit and logic design
* Able to preform functional and timing verification for circuit and logic design
* Understanding C and Perl programming.
* Familiar with EDA tools from Synopsys, Cadence, like NC-Verilog, VCS, DC/PC or PrimeTime
* Familiar with digital video processing or DSP design is a plus but not required
* Good written and oral English communication skills
* Good team work spirit, easy to cooperate with team members
Verification Engineer

Department: ASIC

Title: Verification Engineer

Justification: Support verification for new designs in MMP2, such
as ebook controller, ISP verification.


Job Description:

- Build test environment and develop test cases.

- Run power simulation.

- Run gate level simulation.


Qualification:

- Familiar with verilog and C.

- Familiar with system verilog, synthesis are plus.

- Knowledge of perl is a plus.

BS or MS are required

- 2-3 years experience are plus.
发表于 2010-9-15 23:22:15 | 显示全部楼层
好消息,可信吗?
谁试过?
发表于 2010-9-16 20:11:04 | 显示全部楼层
不了解
发表于 2010-9-16 22:37:27 | 显示全部楼层
ddddddddddddddd
发表于 2010-9-17 07:22:30 | 显示全部楼层
待遇如何?、
发表于 2010-9-22 20:22:12 | 显示全部楼层
bu ke xin !
发表于 2010-9-25 20:38:52 | 显示全部楼层
应届硕士 9.5K,工作3-5年硕士 15K,而且公司公积金之类的全部交
发表于 2010-9-25 22:31:54 | 显示全部楼层
回复 7# star_ic


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