HIGH POWER-SUPPLY REJECTION CURRENT-MODE LOW-DROPOUT LINEAR REGULATOR

hi_china59

HIGH POWER-SUPPLY REJECTION CURRENT-MODE LOW-DROPOUT LINEAR REGULATOR

Georgia Institute of Technology, May, 2009

TABLE OF CONTENTS

CHAPTER 1
INTRODUCTION 1
1.1 Power Management Overview 1
1.2 Linear Regulators 3
1.3 Relevant LDO Characteristics 5
1.4 LDO Design Challenges 8
1.5 Research Objective 11
1.6 Synopsis 12 2 POWER SUPPLY REJECTION IN LDO REGULATORS 13

CHAPTER 2
2.1 PSR Analysis 13
2.2 Supply Ripple vs. Spikes 16
2.3 State of the Art 17
2.4 Proposed Current-Mode Architecture 21
2.5 System-Level Current-Mode LDO Regulator 22
2.6 Synopsis 24

CHAPTER 3
3 CURRENT-MODE LDO REGULATOR IC 25
3.1 Transistor-Level Implementation 25
3.2 Stability Analysis 26 3.3 PSR Analysis 32
3.4 Achieved Design Performance and Layout Challenges 36
3.5 Synopsis 37

CHAPTER 4
4 EXPERIMENTAL RESULTS AND CONCLUSIONS 39
4.1 PCB Design and Testing Environment 39
4.2 PSR Measurement Results 40
4.3 Transient Measurement Results 42
4.4 Evaluation of the Proposed Architecture 45
4.5 Conclusions 47 4.6 Recommendation/Future Research 49

APPENDIX A: MATHEMATICAL ANALYSIS OF DUAL-LOOP FEEDBACK SYSTEMS 50
REFERENCES 52

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jackal0716

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bluesmaster

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apherma

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wangwang1

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