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发表于 2007-1-15 13:03:16
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Abstract— This paper presents a two-stage, compact, powerefficient
3 V CMOS operational ampiifier with rail-to-rail input
and output ranges. Because of its small dle area of 0.04 mmz, it is
very suitable as a VLSI library cell, The floatlng class-AB control
is shifted into the summing circuit, which results in a noise and
offset of the amplifier wh]ch are comparable to that of a three
stage amplifier. A floating current source biases the combined
summing circuit and the class-AB control. This current source
has the same structure as the class-AB control which provides a
power-supply-independent quiescent current. Using the compact
architecture, a 2.6 MHz amplifier with Miller compensation and
a 6.4 MHz amplifier with cascoded-Miller compensation has been
realized. The opamps have, respectively, a bandwidth-to-supplypower
ratio of 4 MHz/mW and 11 MHz/mW for a capacitive
load of 10 pF. |
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