发一篇设计内容非常全乎的关于全差分运放设计的论文（共105页）

raingosi

发一篇关于一个全差分运放设计的论文（共105页），所设计内容非常全乎！包括运放十多项指标的定义及其各项指标（SR，PSRR，Noise等等）的分析与设计实现，
CMFB设计，稳定性补偿，谐波抑制，版图设计，电路仿真分析，工艺变化与不匹配问题等等。
Table of contents:
1. Introduction ................................................................................................................................8
1.1 Introduction ...............................................................................................................................8
1.1.1 General considerations...........................................................................................................8
1.1.2 ADC Definition and characterization ....................................................................................9
1.2 The use of operational amplifier in ADC topology...................................................................9
1.3 The need of high specifications...............................................................................................10
2. Specifications........................................................................................................................... 11
2.1. Signal to Noise Ratio (SNR) definition..................................................................................11
2.2 Signal Distortion to Noise Ratio (SNDR) definition.............................................................12
2.3 Power Supply Rejection Ratio (PSRR) definition..................................................................12
2.4 Common Mode Rejection Ratio (CMRR) definition..............................................................12
2.5 Power dissipation....................................................................................................................13
2.6 Slew rate.................................................................................................................................13
2.7 Settling time............................................................................................................................14
2.8 Noise.......................................................................................................................................14
2.8.1 Thermal noise........................................................................................................................15
2.8.2 1/f (flicker) noise...................................................................................................................15
2.9 Spurious free dynamic range...................................................................................................16
2.10 Open loop DC gain.................................................................................................................16
3. Theoretical approach of operational amplifier..........................................................................18
3.1. Simple single ended operational amplifier.............................................................................18
3.2. Full differential operational amplifier.....................................................................................20
3.2.1 General topology..................................................................................................................21
3.2.2 Common mode feedback (CMFB) topology.......................................................................21
3.2.2.1 Understanding the need of CMFB....................................................................................21
3.2.2.2 Continuous time CMFB....................................................................................................23
3.2.2.3 Sensing structure...............................................................................................................24
3.2.2.4 Comparator design.............................................................................................................26
3.2.2.5 Switched capacitor CMFB................................................................................................27
3.2.2.6 Switch care.........................................................................................................................29
3.2.2.6.1 Dummy switch................................................................................................................30
3.2.2.6.2 Complementary switch...................................................................................................30
3.2.3 Slew rate..............................................................................................................................30
3.3 Folded cascode structure........................................................................................................31
3.3.1 Topology description............................................................................................................31
3.3.2 Gain calculation....................................................................................................................32
3.4 Telescopic structure.................................................................................................................34
3.4.1 Noise consideration..............................................................................................................35
3.4.2 Gain boosting.......................................................................................................................37
3.5 Two stage topology.................................................................................................................39
3.5.1 Miller compensation.............................................................................................................39
3.5.2 Zero pole compensation.......................................................................................................42
3.5.3 Noise consideration..............................................................................................................43
3.6 Conclusion and choice.............................................................................................................44
3.6.1 Overall topology choice: 2 stage op amp.............................................................................44
3.6.2 Compensation method..........................................................................................................45
3.6.3 Common Mode Feedback choice.........................................................................................46
4.Implementation..........................................................................................................................47
4.1. Schematic and simulations.....................................................................................................47
4.1.1. Input stage..........................................................................................................................47
4.1.1.1 NMOS input transistor......................................................................................................47
4.1.2. Gain boosting.......................................................................................................................49
4.1.3. Output stage........................................................................................................................50
4.1.4. Common mode feedback (CMFB) circuit...........................................................................51
4.1.4.1 CMFB compensation network..........................................................................................51
4.1.5. Compensation.....................................................................................................................53
4.1.6. Overall topology and simulations.......................................................................................54
4.1.7 Spectral analyze...................................................................................................................56
4.1.7.1 Spurious Free Dynamic Range.........................................................................................56
4.1.7.2 Third harmonic rejection and output dynamic range.........................................................57
4.1.8 Slew rate..............................................................................................................................58
4.1.9. Power Supply Rejection Ratio (PSRR)...............................................................................58
4.1.10 Noise analyse results...........................................................................................................59
4.2. Layout....................................................................................................................................61
4.2.1. Layout considerations.........................................................................................................62
4.2.1.1. Common centroide structure............................................................................................62
4.2.1.1.1 One dimension approach................................................................................................62
4.2.1.1.2 Two dimensional common centroide structure..............................................................63
4.2.1.2. Gate shadowing limitation...............................................................................................64
4.2.1.2.1 Source of the gate shadowing problem..........................................................................64
4.2.1.3. Dummy structure..............................................................................................................64
4.2.1.4. Rooting care......................................................................................................................66
4.2.1.4.1 Dummy lines...................................................................................................................66
4.2.1.4.2 Contact size and layers width.......................................................................................67
4.2.1.5. Minimum gate finger number...........................................................................................68
4.2.2. Actual layout........................................................................................................................68
4.2.2.1 Input stage.........................................................................................................................68
4.2.2.2 Output stage......................................................................................................................70
4.2.2.3. Overall layout of the operational amplifier......................................................................71
4.3 Layout Versus Schematic (LVS)...........................................................................................71
4.4. Post layout simulation............................................................................................................74
4.4.1. Worst case simulation.........................................................................................................75
4.4.1.1 Worst Power simulation....................................................................................................77
4.4.1.2. Worst Speed simulation...................................................................................................77
4.4.1.3 Worst Zero simulation......................................................................................................78
4.4.2 Other model..........................................................................................................................78
4.4.3. Monte Carlo simulations.....................................................................................................78
4.4.3.1. Process variations............................................................................................................80
4.4.3.2. Mismatch variations.........................................................................................................80
4.4.3.3 Process and mismatch variations.....................................................................................82
5. Conclusion and outlook..............................................................................................................86

raingosi

我个人感觉挺好的运放设计论文，强烈举荐！

muyangtong

cjlmxl

Thank you very much!!

fanjx

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colinwang

iyahsue

goooooooooooooooooooooooooooooood

liweifb

xiexie  bucuo

asueee1

thanks

liuzhieetop