Testing and Design-for-Testability (DFT) for Digital Integrated Circuits

邝卓宇 · 发表于 2024-5-20 09:18:15

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IEP_C2SD_2017_HR.pdf (1.17 MB, 下载次数: 110 )
Hafizur Rahaman(hafizur@vlsi.iiests.ac.in)School of VLSI TechnologyIndian Institute of Engineering Science and Technology (IIEST), ShibpurIndiaIEP on Introduction to Analog and Digital VLSI Design held at IIT Guwahati on 13th April 17

95页的PPT，比较全