一篇讲高速接口 Rx Tx CDR的论文

zhang_pting

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DESIGN OF HIGH-SPEED SERIAL LINKS IN CMOS

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DESIGN OF HIGH-SPEED SERIAL LINKS IN CMOS

Chapter 1 Introduction......................................................................................................1
1.1 CMOS Links ...........................................................................................................1
1.2 Link Components....................................................................................................3
1.3 Organization............................................................................................................4
Chapter 2 Background ......................................................................................................7
2.1 Fan-out-of-four Delay Metric for Bit-time .............................................................8
2.2 Bit-error Rate ........................................................................................................10
2.2.1 Amplitude noise ..........................................................................................11
2.2.2 Timing noise ...............................................................................................14
2.3 Example of a Basic Link.......................................................................................16
2.3.1 Channel .......................................................................................................17
2.3.2 Transmitter..................................................................................................19
2.3.3 Receiver ......................................................................................................23
2.3.4 Timing recovery..........................................................................................27
2.4 Employing Parallelism..........................................................................................
2.5 Summary...............................................................................................................34
Chapter 3 Parallelized I/O Circuits................................................................................37
3.1 Transmitter Design................................................................................................38
3.1.1 Intrinsic RC limitation ................................................................................40
3.1.2 Minimum select pulse-width limitation ......................................................43
3.1.3 Implementation ...........................................................................................47
3.1.4 Scalability ...................................................................................................51
3.1.5 Transmitter summary ..................................................................................53
3.2 Receiver Design ....................................................................................................53
3.2.1 Sampler design............................................................................................54
3.2.2 Comparator design ......................................................................................62
3.2.3 Second-order receiver-design issues...........................................................66
3.2.4 SR-latch design ...........................................................................................68
3.2.5 Scalability ...................................................................................................69
3.2.6 Receiver summary ......................................................................................70
3.3 Summary...............................................................................................................71
Chapter 4 Clock Generation and Timing Recovery .....................................................73
4.1 Clock Generation ..................................................................................................74
4.1.1 VCO design.................................................................................................75
4.1.2 Loop design.................................................................................................78
4.1.3 Jitter.............................................................................................................86
4.2 Multiple-Phase Clock Generation.........................................................................86
4.2.1 Interpolation................................................................................................87
4.2.2 Device-and-layout mismatches...................................................................92
4.2.3 Modulated noise..........................................................................................94
4.2.4 Measured results .........................................................................................96
4.2.5 Summary .....................................................................................................99
4.3 Timing-Recovery Architectures............................................................................99
4.3.1 Phase-locked loop-based timing recovery ................................................100
4.3.2 Phase-picking-based timing recovery .......................................................104
4.4 Timing-Recovery Implementation......................................................................106
4.4.1 Decision algorithm and implementation...................................................107
4.4.2 Handling frequency offset.........................................................................111
4.5 Summary.............................................................................................................112
Chapter 5 Experimental Results...................................................................................115
5.1 Channel ...............................................................................................................116
5.1.1 Cable and PCB..........................................................................................116
5.1.2 Packaging..................................................................................................118
5.1.3 Noise issues...............................................................................................119
5.1.4 On-chip termination ..................................................................................121
5.1.5 Channel characteristics .............................................................................122
5.2 Transceiver Test Chip .........................................................................................124
5.3 Transmitter Experimental Results.......................................................................127
5.4 Receiver Experimental Results ...........................................................................129
5.5 Transceiver Experimental Results ......................................................................131
5.5.1 Bit-error-rate measurements .....................................................................131
5.5.2 Jitter and phase tracking............................................................................136
5.6 Summary.............................................................................................................138
Chapter 6 Conclusion ....................................................................................................141
6.1 Scaling Trends ....................................................................................................143
6.2 Future Work ........................................................................................................145
Appendices.....................................................................................................................149
Bibliography ...................................................................................................................

zhang_pting

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