【全职招聘】AMD 上海各职位招聘工程师！（热招！！！）

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1、Memberof technical staff for IC design verification (MTS DV)

Requirements:

Thecandidate is preferred to be MSEEwith minimum of 6 years, or BSEEwith minimum of 8 years experience indigital ASIC/SOC design verification.  

Thecandidate must have:

1.
deep understanding on ASIC/SOC design flow

2.
Excellent knowledge ofdesign verification methodology, such as VMM or OVM and UVM.

3.
Solid experiences with simulation model creation and the testbenchbuild

4.
Strong RTL coding with Verilog

5.
Strong SystemVerilog experiences.

6.
Strong C/C++ software development experiences

7.
Be good at scripting language, such as Perl, Cshell, Ruby, and Makefile.

It is a must that the candidate has one or more of thefollowing experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB)bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCIbus, low power design, clock generation and control, SD/eMMC host controller,SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), Ethernet, JTAG, etc.

Thecandidate is expected to exhibit good verbal and written communication skillsin both Chinese and English, specialized knowledge plus broad technicalknowledge that facilitates integrative thinking, , driving execution of qualityand timely result, capability  to solvecomplex, novel and no-recurring problems and decision-making on criticaltechnical areas

Hands-onlab experience is another plus, able to understand and/or use the use scopes,logic analyzers, has knowledge or skill of board-level lab debugging.

Responsibility:

Thesuccessful candidate will work with team members and apply current functionalverification techniques to perform and improve pre-silicon verification qualityand product Time to Market for Southbridge design. The candidate will providethe technical leadership to the DV team for the new Southbridge project. He/Sheshould be able to work independently on various DV tasks and providingtechnical guidance to the DV team. The candidate would involve technically inthe porting/creation of the DV environment for the new design, block and chiplevel test plan creation and implementation, coverage analysis, and regressioncleanup.

2、FCHDriver/OS Architect(PMTS)

Area of  Interest:	Software Engineering
Job Title:	FCH Driver/OS Architect(PMTS)
Location	Sunnyvale or Shanghai
Country:	US or China
Job Description:            DESCRIPTION OF DUTIES:    - Architect, design and guide the implementation of  all Windows and Linux software- ranging from kernel, middleware to application    - Understanding current and planned hardware  functionality and be able to define software directions aligned with silicon  features    - Distill industry and technology trends into  actionable software (and hardware) deliverables    - Working with senior architects and fellows  across AMD to ensure that our technical directions are aligned with other  areas of the corporation    - Working with  management team to understand, clarify, and shape requirements, and to  translate these into technical requirements used to design the product   - Regular communication via  Audio/Video conference with Global Teams          PREFERRED EXPERIENCE:    - MS-EE/MS-CS with at least 10 years’ experience  in Windows/Linux system development, or 7 years’ experience for PHD degree    - Excellent and demonstrable C/C++ programming skills    - Deep understanding of x86 architecture    - Strong kernel, device driver development  experience, Linux  kernel or Windows device driver experience is a plus    -  Deep understanding on at least one controller in South Bridge (SATA, USB,  etc) or power management under X86 architecture    - Strong analysis  and problem solving skills required    - Experienced  project planning and prior technical leadership responsibilities    - Proven  interpersonal skill, technical leadership and teamwork required    - Must be fluent  in both written and spoken English    - Experience  working with multi-site teams preferred

3、JD:MTS/SE for Camera/ISP SW Development (Windows)

PREFERRED EXPERIENCE:

- BS-CS/BS-EE with at least 7years’ experience in Windows device driver development, or 5+ years’ experiencefor MS

- Good at C/C++ language, demonstrable C/C++programming skills

- Experience with WindowsAVStream Framework or Multimedia driver

- Solid understanding of WindowsDriver Architecture (WDM/WDF)

- Experience with ISP, camerasensor tuning activity.

- Good understanding ofembedded system and/or tablet architecture is a plus

- Knowledge in ISP(Image SignalProcessing), video encoding/decoding is a plus

- Strong analysis and problemsolving skills required

- Proven interpersonal skill,technical leadership and teamwork required

- Fluent in both written andspoken English
- Experience of working with multi-site teams preferred

KEY Responsibilities:

- Architect, design andimplement Windows Camera/ISP solutions for AMD Platform Solutions

- Closely interact with ASIC designteam in new feature definition and bring up for future product generation

- Improve customer satisfactionand product quality by solving technical problems

- Accountable on time deliveryof deliverables

- Collaborate and interfacewith local and global management, development and test teams to deliver acomplete product solution

- Regular communication viaAudio/Video conference with global teams

4、JobDescription

Position Title		Sr. Fro-end ASIC Design CAD  engineer
Organization	Technology  and Engineering		Function	CAD
Location	Shanghai		Rep/Add	Rep

Position Summary

l
Participate in the design and implementation of the leading edge,front-end ASIC design flow

l
Participate in the research of Design Methodology to improve automationand  productivity to produce AMD's newhigh-quality cutting-edge APU and GPU products

l
Technical support and programming

l
Interface with EDA vendors on technology

Key Relationships

Reports To: Angela Xue

Direct Reports: Angela Xue

            

Peer Relationships:      

Other Relationships:      

                                                        

Essential Functions:

EssentialRequirements/Qualifications:

1.
Major in EE, CS or related, Master Degree with 3+ years orBachelor with 5+ years working experience

2.
Experience in Front-end digital design and VerilogHDL is required

3.
Good programming skill with one or more languages (e.g. Tcl, Perl,python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow

4.
Familiar with SRAM design and behaviour is a plus

5.
Familiar with one or more ASIC flows (logic synthesis, STA etc.)and usage of related EDA tools is a plus

6.
Good written and spoken English

7.
Good communication skills and be able to work both independentlyand in a team

5、JD:MTS/SE for Camera/ISP SW Development (Android)

PREFERRED EXPERIENCE:

- BS-CS/BS-EE with at least 7years’ experience in Android/Linux device driver development, or 5+ years’experience for MS

- Good at ARM assembly and C/C++ language,  demonstrableC/C++ programming skills

- Experience with Android cameraHAL, camera service programming.

- Experience with Androidmultimedia OpenMAX framework integration.

- Experience with Androidkernel V4L2, camera sensor, VCM and flash driver programming.

- Experience with ISP, camerasensor tuning activity.

- Good understanding ofembedded system and/or tablet architecture is a plus

- Strong analysis and problemsolving skills required

- Proven interpersonal skill,technical leadership and teamwork required

- Fluent in both written andspoken English
- Experience of working with multi-site teams preferred

KEY Responsibilities:

- Architect, design andimplement Linux/Android Camera/ISP solutions for AMD Platform Solutions

- Closely interact with ASICdesign team in new feature definition and bring up for future productgeneration

- Improve customer satisfactionand product quality by solving technical problems

- Accountable on time deliveryof deliverables

- Collaborate and interfacewith local and global management, development and test teams to deliver acomplete product solution

- Regular communication viaAudio/Video conference with global teams

	6、Senior  Staff/Staff Design Lead for  Wired  Connection IP
City/Town:	Shanghai
Country:	China

- Participate IP and SoClevel architecture definition, create IP architectural spec, derive functionaland design specifications and analyze feasibility of technical andarchitectures.

- Implement design withVerilog to achieve specification goals. Simulate and debug the codes in codingstage.

- Define timingconstraints and support the FE Integration team to deliver qualified netlist.Feedback to Physical Design team to help to close timing and check floorplan

- Discuss with SW team togenerate an optimized HW/SW partition of the functionalities

- Support FW/SW bring-upand debugging

- Working as thetechnical point of contact in the Wired Connection IP area.

- Maintain designenvironment, solve flow issues, and develop scripts to improve flow efficiency.

                                                        

Essential Functions:

Architecture, RTL, Synthesis, STA, Timing Analysis, Constraints

Essential Requirements/Qualifications:

- Proven IP / SoC Design / Integration Experience

- Must have strong background on IP development

Desired:

- Enthusiasm on technical topics

- Major in EE & CS

- Must be proficient in Verilog coding, debugging and modeling

- Deep understanding of below technical aspects wouldbe an asset:

·
10GbE+ solutionsfrom the industry leading companies

·
basic offloadengines used in 10GbE/40GbE, such as

o
TCP transmitsegmentation offloading

o
TCP Large receiveoffload

o
Receive sidescaling

·
Basic filteringand Classification: Unicast/multicast/broadcast, ACLs

·
Advancedfiltering and classification: flow based and L3 protocol based

·
Data-centerbridging, PFC/ETS/DCBX/QCN

·
Devicevirtualization, SR-IOV/VEB/VEPA

·
Advanced offloadengine

o
TCP offload: TOE

o
Storage offload:iSCSI HBA/FCoE HBA

o
RDMA: RoCE/iWARP

o
Security offload:IPSec

- 10 gigabit+ Ethernet IP design experience would be an asset

- Ethernet HW/SW performance analysis experience wouldbe an asset

- Befamiliar with ASIC design flow, such as synthesis, DFT, timing analysis, ECOetc

- Be familiar with shell/perl/tcl programming in linux OS.

- Should have strong problem solving skills

- Good English hearing, speaking, reading and writing capabilities

- Goodcommunication skills

- Have mass production tape‐out experience