【全职招聘】AMD 上海热招各职位人才！

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1、Senior /MTS Engineer of Physical Design

PositionTitle      Senior /MTS Engineer ofPhysical Design

Organization      Shanghai R&D Center     Function              SCBU

Location               Shanghai, China                Rep/Add              Add

Job Description:           

Work with global Front-End design team andphysical design team for large scale ASIC chip physical implementation. Focuson physical design of deep sub-micron GPU chips including block level (fullchip) floor planning, timing closure, place&route, physical verificationetc. The individual is expected to be an expert in multiple aspects in PD areasand provide technically leadership to the engineering team. The individual isalso expected to be accountable for project delivery.

Job Requirement:

1.
MSEEwith 6+ years or Bachelor with 8+ years of industrial experience in ASICdesign

2.
5+years or more years of experience in physical design of deep submicron digitalASIC chips

3.
Handson experience in large scale ASIC chip physical design

4.
Knowledgeablein all aspects of deep submicron ASIC design flow

5.
Successfullygone through several complete product development cycles

6.
Demonstratestrong leadership and work well with cross-functional teams

7.
Goodlistening, writing and speaking English

8.
Goodcommunication skills, strong interpersonal skills and the flexibility

9.
Dedicated,hard working and good team player

10.
Familiarwith Back-End (physical design) EDA tools

11.
Familiarwith Front-End EDA tools is a plus

12.
Familiar with Unix/Linux environment and goodat scripts

13.
Sr./MTS Logic Design Engineer

14.
Location: Shanghai

2、MTSLogic Design Engineer

DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
1. Develop micro-architecture specification for block/IP implementation
2. Write RTL code in Verilog-HDL and drive Verification
3. Perform ASIC synthesis, netlist generation, block and chip level timinganalysis
4. Guide Physical Place and Route.

PREFERRED EXPERIENCE:
1. MSEE with 5+year or BSEE with 8+ years of industry experience in deepsubmicron ASIC design and verification.
2. Expertise with HDL and design of high speed and high complexity digitallogic required
3. Experience with SOC Integration and Place and Route(a plus)
4. Expertise of Computer Architecture and computer Arithmetic (a plus)
5. Expertise of Computer Graphic and HW implementation(a plus)
6. DDR-SDRAM/PCI/PCI-e experience(a plus)

3、Engineer/Seniorfor GPU Integration   (5)

Job  Title:	Engineer/Senior  for GPU Integration   (5)
City/Town:	Shanghai
Country:	China
Recruiter	zoe.yu@amd.com
Job  Description:	Responsibility:    · Integrate  GPU blocks as chip based on architectural requirement.    · Develop  RTL code for macro blocks in Verilog HDL and make sure functional correct and  reusable for different configuration.    · Synthesis  and deliver netlist that meeting timing, area and power requirement. Help PD  on the floorplanning and close timing.       Requirement:    · MS  degree of EE with 1~ 4 years, or bachelor with 3~7 years working experience  in ASIC Company.      · Familiar  with Verilog RTL design and has experience of large digital ASIC project.    · Familiar  with front-end EDA tools and flows (Design compiler, PrimeTime,  Conformal,Verde)    · Familiar  with unix/linux and scripts (tcl, perl etc.)    · Fluent  English on talking, presentation and writing documents.      · Strong  sense of task scheduling and deliver on time as predetermined milestones  committed to manager.            5、MTS for  GPU Integration   (1)         Job Title:                MTS  for GPU Integration   (1)    City/Town:             Shanghai    Country:                China    Recruiter               zoe.yu@amd.com       Job Description:   Responsibility:    •              Define  GPU chip level specification, including clock and power targets, IP  selection, floorplan review, package definition, PCB spec etc.    •              Estimate  GPU performance and TDP before ASIC bring-up. Provide regarding information  to make up test plans.    •              Communicate  with design and marketing teams to define bounding-box for SKU volumn split.    •              Bring-up  ASIC. Guide hardware team to solve design problem in application. Help to  short Time-To-Market.       Requirement:    •              MS  degree of EE with more than 5 years working experience in ASIC Company.      •              Familiar  with Verilog RTL design and has experience of large digital ASIC project.    •              Experience  for ASIC tapout and bring up.    •              Fluent  English on talking, presentation and writing documents.      •              Strong  sense of task scheduling and deliver on time as predetermined milestones  committed to manager.          Title: MTS ASIC Design Verification Engineer - SoC    Req Number:      Location: Shanghai/Beijing, China    Department: SCBU    Hiring Manager:    Recruiter:       AMD’s SCBU APU Design Verification team is looking for  highly motivated Verification Engineers to work on next generation APU SoC  development.          KEY RESPONSIBILITIES:       -               Work  closely with the SoC design team on understanding the APU system features  being designed;    -               Develop  and execute test plans for system level functional features related to Memory  Controller/ Power Management/ Coherency / Security / Multi-Media …etc.    -               Design,  implement and improve verification testbench in Verilog, System-Verilog,  C/C++, OVM;    -               Develop  and refine test libraries, model and test cases;    -               Apply  functional coverage/assertion into testbench as enhancement;          REQUIREMENTS:       -               At  least 5 years DV experience with good understanding on IP level verification  and system level verification;    -               Good  understanding on C/C++/Perl/Shell language;    -               Have  experienced at least 1 complete production cycle;    -               Be  fluent in English speaking and writing    -               Self  motivated;         6、MTS  Design Engineer - DFT      Position: MTS Design Engineer - DFT       Job Description:       Qualified  candidate will perform some or all functions below:       1. Participate in SOC full Chip DFT feature and  architecture definition    2. Responsible for DFT specification generation and review    3. Implement SOC DFT function including SCAN, Boundary  SCAN, MBIST, Analog Macro test logic.    4. Perform verification on all DFT structures    5. Generate DFT related timing constraints and work with  PD team for timing closure    6. Generate and verify DFT structural patterns and  functional patterns    7. Participate in ATE bring-up and debug the DFT patterns  on ATE    8. Design and implement other DFX (debug,  characterization, yield etc) logics                                                                   Requirements/Qualifications:                -    BS in EE & CS.  MS preferred,  with 4+ years experience.    -   Hands on working experience on ASIC DFT  design and verification   -   Familiar with entire ASIC design  flow    -   Experience with micro processor design a  big plus    -   Should have strong problem solving skills   -   Good English hearing, speaking, reading  and writing capabilities    -   Good communication skills      7、MTS/Senior  Software Development Engineer         Job Title: MTS/Senior Software Development Engineer    Windows/Linux Graphic  Base Driver    ROLE &  RESPOSIBILITIES          - Work as part of the global SCBU SW engineering team to design  and maintain the graphics device driver    - Resolve problem reports related to graphics device driver  including troubleshooting, debugging, & defect correction    - Specify, design and implement software stack for new ASIC or per  customer requirement    - Coordinate closely with peers at both Asia and North America to  ensure timely and effective communication of all assigned work activities.    - Responsible for the Diagnostic and verification for HW features  of new ASIC    DESIRED EXPERIENCE:    - Experience in multi-threaded programming in a x86 or ARM architecture  in both kernel & user modes.    - Object-oriented design & programming    - C/C++ programming    - Experience with Windows or Linux/Android kernel driver  programming on either x86 or ARM system    - Experience with software debugging and related tool such as  WinDbg or gdb in an x86 architecture in both kernel & user modes is a  plus    - Experience with software development on Android platform(Graphic  system, Multimedia system and etc.) is a plus    - Min. 3 years direct experience in Windows or Linux graphics driver  development is preferred    - Experience in Low-level programming of hardware devices is  preferred    - Experience with graphic or display technologies (DisplayPort,  HDMI, Stereo 3D display, wireless display, etc.) is a plus          DESIRED KNOWLEDGE, SKILLS  & CHARACTERISTICS    - In depth understanding of PC or embedded system architecture    - In depth understanding of Operating System architecture    - Good software debugging logic and hands on knowledge    - Good verbal and written communication skill    - Excellent multi-tasking and prioritization skill    - Good team works    - Self motivated, strong initiative, can work under moderate to  minimal supervision      EDUCATION    - BA/BS degree with strong  academic background or equivalent experience (higher level degree a plus) in  Computer Science, Electrical Engineering, Software Engineering. MS or PHD is  a plus.            8、ISP IP System  Engineer      Location:  Shanghai       [Responsibility]    1. Support  ISP Pre-silicon emulation    2. Extract  the feature list with design teams and from internal documents;    3. Generate/maintain  the detailed post silicon test plan for ISP IP enablement and optimization by  cooperating with the complete cross-functional teams;    4. Generate  the bring up plan with ISP bring up teams to collect, monitor and track the  bring up execution status updates.      5. ISP  related issues debug/track/ close, including HW/SW issues, internal/customer  issues;    6. Cooperate  with ISP validation to generate the validation test plan;       [Requirement]    1. Experience  with image sensor or products containing ISP;    2. Solid  knowledge in optical system, imaging and image quality;    3. Good  understanding of the chip design, implementation, and bring up processes;    4. Excellent  communication and leadership skills among different functional teams;    5. Experience  in HW, SW, and system level debugging and triage;    6. Familiar  with semiconductor reliability;    7. Experience  in risk assessment and mitigation methodology.    8. Fluent  English both oral  and written;    9. Master  degree      9、ISP  tuning engineer      Location:  Shanghai       [Responsibility]    1. Image  Sensor/sensor module calibration and tuning for AMD’s ISP;    2. Image  quality assessment, fine tuning, and certification for AMD and AMD’s  customers;    3. Calibration/tuning  tool chain development and process documentation;       [Requirement]    1. Solid  knowledge in optical system, imaging and image quality;    2. Strong  C/C++ and Matlab programming skills;    3. Experience  in mobile camera/sensor calibration/tuning process;    4. Familiar  with image and color processing techniques, include 3A(AWB, AE, and AF),  gamma correction, demosaicing, denoising, WDR and etc.    5. Familiar  with image quality certification process is a plus;    6. Master  degree      10、Sr.  Program Manager   Job Description:    The individual who  fills this role will be responsible for driving GPU (Graphics Processing  Unit) programs from product definition through SOC (system on chip)  development to full deployment. This individual will lead a cross-functional  product development core team, aligning all aspects of engineering and  operation execution to meet business goals. This individual will interact  with AMD executives and senior management team, internal cross functional  teams, 3rd-party partners, and possibly customers. This individual will be  responsible for the management of program execution and its day-to-day  activities centered around GPU development. This individual will work with  engineering management to drive execution excellence, including key metrics  like Time-to-Market, Time-to-Yield, and Time-to-Volume. This individual will  work collaboratively with AMD Program Management community on infrastructure  development and continuous process improvement. Work is strategic in nature,  but hands-on work on tactical manners is definitely expected. While based at  AMD Shanghai site, this individual will have substantial interactions with  key contributors from AMD North America sites. Communication is a critical  part of this role which includes interpreting/understanding business directions,  explaining tactical details, and recommending solutions regarding complex  program situations. Some travel is expected for this role.      Job Requirements:    · Experience is required in managing large, complex,  interrelated projects, programs, and functions.    · Experience in large scale ASIC development, plus working  knowledge across multiple engineering disciplines (e.g. board design and  testing, thermal management, packaging design and qualification, product  engineering, software development and qualification) is highly desirable.    · Experience in operations, product marketing, and/or product  management is a plus.    · Ten years minimum related experience with five years program  management experience. Seeking candidates who are result-driven, disciplined,  and analytical, who demonstrates good problem solving skills, interpersonal  skills, communications skills, and teamwork spirit.    · Bachelor of Science (required) in Electrical Engineering, and  Masters of Science (preferred) in other engineering disciplines.      11、Title:  SMTS /PMTS as SOC chip architect      Job  Scope:    l Translate the customer chip requirement into  SOC architecture and define the architecture specification accordingly    l Reconcile all IP domain architects to scope  the feature implementation efforts and gauge the trade-off between feature  and resource/schedule    l Ensure the chip bounding  box(Pin/Area/Power/Performance ect) is properly projected and achieved by  meeting customer definition    l Monitor the project execution and co-work with  verification/DFT/PD architects to assure the chip is right on the track for  all architectural parameters.    l Provide the chip architectural support to  software team.       Job  Qualification:    l Master with 10 years + and bachelor with 13  year+ IC industrial experience on chip architecting, IP/subsystem  micro-architecting or chip design leadership.    l Strong chip-based know-how like  pin/package/performance/power/area.    l Multiple chip tape-out is a preference.    l Good understanding of IP knowledge(GFX/Multimedia/CPU/Bus)  is a plus    l Exposure on process node is a bonus    l Communicative and interpersonal with solid  driving and leading capability    l Good verbal and written English         12、Title:  SMTS as Chip Top Design Lead         Job  Scope:    l Scope the top design components and lead the  top design efforts for customized chip.    l Explore the design and spec the implementation  of the third-part IP into company interconnect    l Handle the chip pervasive logic on the top  like power/clock/reset.    l Responsible for the  hookup/modification/build-up for all chip connectivity    l In charge of top design lib/code changes for  process-node conversion    l Support the chip integration team from the top  view.       Job  Qualification:    l Master with 8 year+ and bachelor with 10 year+  industrial experience on bus/interconnect, power control unit, clock  generator, reset controller and protocol conversion like bridge/FIFO etc.    l ARM-based protocol(AXI/AHB/APB) is a preference  and other in-house bus protocol is a bonus    l Understanding of process evolvement and impact  to the design is a big plus    l Very strong RTL coding and sense of  timing/area/layout impact to design    l Good verbal and written English    l Communicative and interpersonal with solid  driving capability      13、Title: Senior  MTS ASIC Design Verification Engineer         Req Number: 1 Location: Shanghai, China   Department: SCBU Hiring  Manager: Hank Sun    Recruiter: Zoe Yu       AMD’s SCBU APU Design Verification team is looking for highly motivated  Verification Engineers to work on next generation SOC APU ASIC design.       KEY  RESPONSIBILITIES:       - Define and develop testbench infrastructure and  methodology for AMD next generation APU SOC verification    - Lead the team to enhance the testbench  automation to improve the compiling ,  simulation, debugging efficiency    - Lead the effort of support on EDA tool and  internal tool/flows    - Provide in-depth training and efficient  support to whole SoC Design/Verification team    - Link with EDA vendor for lead-edge  tools/flow/methodology evaluation and implementation    - Co-work with Emulation team for reusable DV  components development             REQUIREMENTS:    - Minimum 8+ years Design Verification  experiences,  at least have 3+ years of DV experience at SOC level    - Strong experience on building system level  testbench from scratch    - Very good understanding on verilog, systemverilog,  c, c++, Pli, Dpi, Perl    - Rich background on OVM/UVD methodology is a  big plus    - Need to know well about the testbench  automation and able to speed up the verification progress using script    - At least 1 complete production cycle from  concept to mass production    - Having the experience of Arm based SOC  testbench/function DV will be a big plus    - Management  skill-set for small team    - Be fluent in English speaking and writing    -   14、Title: Validation  Manager - Silicon Validation      Location: Shanghai      JOB DESCRIPTION      Silicon validation team manager. In this role, the senior-level manager will:   • Work with technical teams to understand and develop validation plans   • Lead 10-15 person validation team to run tests and evaluate data   • Collect and analyze data from silicon to validate products meet design  specifications   • Lead team to debug test failures to resolution   • Hardware, Software, and Design responsibilities      SKILLS REQUIRED      1) BS-EE / BS-CE / Masters plus at least 10+ years directly related  experience. An advanced degree will be considered a plus.   2) Experience and demonstrated technical expertise in microprocessor  architecture from a test and/or characterization perspective.   3) Experience in leading and managing personnel. Role will have direct and  indirect reporting and will require an inspired leader.   4) Requires excellent written and oral communication skills, to communicate  across a variety of engineering disciplines and between highly-technical  topics and management.         DESCRIPTION OF DUTIES      1) Works directly with global design and validation leadership to understand  validation infrastructure and influence validation plans.   2) Leads and develops a world-class technical team that understands the  unique design implementation details, and then defines the proper tools and  methods to validate that implementation. Works with Validation Team Leads and  External Customers to define Test Plans and expectations.   3) Lead a team to validate the functionality of a design by collecting and  analyzing actual silicon data.   4) Provides detailed reports and explanations to internal technical teams and  external customers to explain measured results.   5) Provides technical guidance and training to grow engineers and technicians  in the planning, test, & analysis of the microprocessor.