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#1 Senior system design engineer
Job description:
The candidate will be responsible for:
? Design and integration an AXI/AHB based system including host processor, DDR controller, SD/MMC, Display I/F and other peripherals., as a verification/demo platform for the in-house designed video IP’s;
? Build up the simulation based environment for the system, for the functional verification;
? Investigate and develop related drivers for the used IP’s in the system;
? Use ISE/Vivado/Quart, implement the design to Altera/Xilinx FPGAs,
? Work with SW engineer, to bring up system/OS on the FPGA prototyping board. Debug and resolve failures with Logic Analyzer and/or ChipScope/SignalTap;
Qualification:
? BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
? Must be highly self-motivator and good team player;
? Good understanding and hands-on experiences in SOC development and related methodology;
? Solid skills in logic design with Verilog/VHDL, timing closure and analysis;
? Familiar with FPGA implementation with ISE/Quartus and debugging;
? Knowledge and hands-on experiences in at least 2 of the below fields are required;
? AXI/AHB bus protocols;
? Design or bring-up of DDR2/3 controller/PHY;
? Display interfaces/protocols such as LVDS/HDMI;
? SD/MMC controller;
? NAND/NOR flush controller;
#2. CPU Verification Intern
Job description:
The candidate will take part in verification for the in-house designed CPU/MCU, including:
? Maintain and improve the verification environment and flow;
? Make the test plan according to the design specification, and execute it with System verilog based coverage monitors/assertions;
? Develop direct tests and constraint random tests;
? Coverage data collection and analysis;
Qualification:
? Graduate student who will graduate in 2015, major in electronic engineering/micro-electronics;
? Must be highly self-motivated, eager to learn and accept new knowledge, a quick learner;
? Could work at least 4 days every week;
? Knowledge and understanding of computer architecture and micro-architecture of RISC processors
? Familiar with front-end ASIC design flow and Verilog HDL;
? Familiar or experiences in high-level verification methodology (VMM/UVM/OVM), and/or hardware verification language (SystemC/SystemVerilog) would be a great plus;
? Experiences or skills in assembly programming, and using scripting languages (Perl/Tcl/Shell) for flow automation is a plus;
#3. (Senior) MCU design and verification engineer
Job description:
The candidate will be responsible for in-house micro-controller design and verfication, including:
? Micro-architecture definition;
? Logic implementation with Verilog HDL;
? Functional verification and performance tuning;
? Synthesis and timing closure;
? Develop direct tests and constraint random tests;
? Coverage data collection and analysis;
Qualification:
? BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
? Must be highly self-motivator and good team player;
? Solid skills and rich experiences in logic design, synthesis and timing analysis;
? Familiar with all front-end flows including LINT check, simulation, synthesis, STA, formal and power analysis, etc.;
? Knowledge and experiences in Computer Architecture and RISC processor (ARM/MIPS/SPARC) micro-architecture, familiar with associated tool-chains such as compiler, assembler, debugger etc.;
? Familiar with CABAC algorithm in video coding standard such like H.264/AVC and HEVC or hands-on engineering experiences in video codec development is a big plus;
E-Mail: bestgrace@qq.com
QQ: 2043753191
新浪blog:
http://blog.sina.com.cn/u/1767088102
新浪微博:
http://weibo.com/bestgrace
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