Cadence SH 招聘资深数字验证工程师

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Cadence SH 招聘资深数字前端验证工程师

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If you have interest, PLS send your update CV to zhangyl@cadence.com

Title:
Principal/Lead Verification Engineer

Position Description:

Deliver/implement IP design. The engineer should be able to act as a strong team member and contributor.

Specific duties include:

- Proficiency in logic design, simulation, synthesis, STA and testing

- Proficiency in Verilog and its simulation environment

At least five years experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment is required.

Position Requirements:

BS degree with 6~10+ years of applicable experience, MS degree with 4~7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics. Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.