招聘数字IC后端设计（PR）人才

沪上小白

上海，硕士5年或本科7年以上数字IC后端设计physical design（PR）职位，以下为职位详细介绍，有意者可加QQ124707482（备注来自eetop）或直接电话联系13661504454 !!!

Position Description:	Perform physical design implementation, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management. The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation physical design, methodology and flow development.
Position Requirements:	BS degree with 5~10+ years of applicable experience, MS degree with 4~7+ years of applicable experience in electrical engineering, microelectronics. Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. Successful track records of taping out complex, 65/40/28 nm SOC chips. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.