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[招聘] 猎头-Sr. Staff / Principal Verification Engineer

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发表于 2013-9-10 21:39:20 | 显示全部楼层 |阅读模式

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Job Title:

Sr. Staff / Principal Verification Engineer

  

Job Description:

As a core member of a SOC development team, primary responsibility will be verification environment development and verification planning and execution. Lead a verification group to accomplish SOC project verification tasks.  


Summary of Duties/Responsibilities:

o            SOC verification requirements analysis and planning

o            Architect and build OVM/UVM based test environment for complex IP and SOC full chip verification

o            Create test plan, and lead the verification organization to implement the verification tasks

o            Design coverage metrics and verification reporting system

o            Coordinate debug efforts to achieve IPs and full chip functionality

o            Documentation of verification, organize/participate in verification/design reviews. Drive verification methodology improvement
  

Job Requirements:

o            Excellent English and Mandarin skills

o            Takes initiative and sets high goals, smart and confident

o            Self starter & ability to work in a team environment as an individual contributor

o            Tracking record of planning and delivering successful verification projects

o            Expert in advanced verification methodology, like OVM, VMM

o            Ability to test silicon using logic analyzers, oscilloscopes, and other common laboratory equipment is a plus.

o            Thoroughly understand SOC development flow, solid knowledge of semiconductor technology

o            Familiar with popular industry protocols, including AHB, USB, I2C, UART, Ethernet, etc.

  

Education & Work Experience:

o         8+ years of verification environment development & SOC verification

o         2+  years of team/project management experience;

o         Expert in System Verilog and OVM or VMM verification methodology

o         Proficiency in Perl, Tcl, Tk, C/C++, Verilog, System Verilog languages

o         Tracking recording of successful SOC product delivery

o         Master's Degree or above in EE/CE

  

Benefits:

o         Competitive salary

o         Stock options

o         Excellent medical insurance plan

o         New product design bonus

o         Extensive training programs covering technology / management skills

  







E-Mail: bestgrace@qq.com

QQ: 2043753191

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发表于 2013-9-11 13:54:37 | 显示全部楼层
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