【猎头职位】physical design engineer/GPU-ASIC-Physical Design Engineer

bestgrace

1. PHYSICAL DESIGN ENGINEER

RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects

MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 2+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power and timing
- Circuit level comprehension of time critical paths, and spice experience a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), CADence (FE/Nanoroute), Sequence (Physical Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred

2.
GPU-ASIC-Physical Design Engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as clocks/timing/convergence/design for test and scripting of flows. You’ll be focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:

- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from Frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.

MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in timing

- Excellent written and verbal communication skills in English

- Ability to multiplex many issues, set priorities, and work in a team environment

- Keep up to date with leading edge technologies

Grace Li

Principal Consultant & General Manager @ Hi-Talent Consulting Co. , Ltd.

上海芯相会企业管理咨询有限公司

E-Mail: bestgrace@qq.com

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