验证职位铺天盖地简历发ic@hi-talent.net

jj_seu · 发表于 2013-8-17 16:34:31

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Memberof technical staff for IC design verification (MTS DV)

Requirements:

Thecandidate is preferred to be MSEE with minimum of 6 years, or BSEEwith minimum of 8 years experience in digital ASIC/SOC design verification.

Thecandidate must have:

1.
deepunderstanding on ASIC/SOC design flow

2.
Excellentknowledge of design verification methodology, such as VMM or OVM and UVM.

3.
Solidexperiences with simulation model creation and the testbench build

4.
Strong RTLcoding with Verilog

5.
StrongSystemVerilog experiences.

6.
Strong C/C++software development experiences

7.
Be good atscripting language, such as Perl, C shell, Ruby, and Makefile.

Itis a mustthat the candidate has one or more of the following experience/knowledge, suchas X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1;SSIC/HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCIbus, low power design, clock generation and control, SD/eMMC host controller,SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), Ethernet, JTAG, etc.

Thecandidate is expected to exhibit good verbal and written communication skillsin both Chinese and English, specialized knowledge plus broad technicalknowledge that facilitates integrative thinking, , driving execution of qualityand timely result, capability to solve complex, novel and no-recurring problemsand decision-making on critical technical areas

Hands-onlab experience is another plus, able to understand and/or use the use scopes,logic analyzers, has knowledge or skill of board-level lab debugging.

Responsibility:

Thesuccessful candidate will work with team members and apply current functionalverification techniques to perform and improve pre-silicon verification qualityand product Time to Market for Southbridge design. The candidate will providethe technical leadership to the DV team for the new Southbridge project. He/Sheshould be able to work independently on various DV tasks and providingtechnical guidance to the DV team. The candidate would involve technically inthe porting/creation of the DV environment for the new design, block and chiplevel test plan creation and implementation, coverage analysis, and regressioncleanup.

贵司有招聘需求的，欢迎和我联系；

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Jane.Jin

Principal Consultant &General Manager @ Hi-Talent Consulting Co.,Ltd.

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