【猎头职位】IC类职位 hot！！！！

bestgrace

IC Design Leader/Manager：

Responsibilities:
1.Lead other Design Engineers in a team to meet the company's objectives
；

2. Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, STA and simulation, chip testing and characterization.

3.This is a full-time position with solid equity opportunity.

Requirements:
1.5+ years of experience in Verilog/Synthesis-based ASIC Design for mass production IC chipsExperience with project and team management
2.Experience from front-end to back-end (RTL, synthesis, verification, and test support) with data networking ASIC(Ethernet, TCP/IP)
3.Verilog language and simulation verification experience
4.Logic Synthesis and Static Timing Analysis
5.Interface with Place and Route and back-annotated simulation verification
6.Team-work spirit, and with a strong drive to excel

IC Design Engineer：

Responsibilities:
1.Work with other Design Engineers to meet the company's objectives；

2.Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, simulation and verification, chip testing and characterization.

3.This is a full-time position with solid equity opportunity.
Requirements:
1.3+ years of experience in Verilog/Synthesis-based ASIC Design
2.Experience with front to back (RTL, synthesis, verification, and test support) with data networking ASIC(Ethernet, TCP/IP)
3.Verilog language and simulation verification experience
4.Logic Synthesis and Static Timing Analysis
5.Interface with Place and Route and back-annotated simulation verification
6.Team-work spirit, and with a strong drive to excel

IC Verification Senior Engineer/Lead：

Responsibilities:
1.Compose the verification plan according to the chip specification and customer's use cases;
2.Adopt the advanced verification methodologies to create the whole verification environment from scratch according to the requirements of specific IC;

3.Design Behavioral functional model and test-benches with C/System C, Verilog/System Verilog and script languages
4.Create, build and implement test cases with high degree of accuracy to verify Device Under Test
5.Work closely with concept architect and RTL designer to verify RTL design through extensive test-bench simulation for modular and top-level design to obtain very high percentage of functional and code coverage

6.Work closely with FPGA prototyping application and validation engineers to verify functional design
7.Coach the inexperienced engineers in the team
8.Secondary task may include design of digital logic with high-level description language (VHDL/Verilog) from specification.
Requirements:
1.Master's/Bachelor's Degree in Electrical/Electronics or Computer Engineering.
2.5+ years IC verification experience on the complex ASIC/SOC
3.Experience with advanced verification methodologies(VMM, OVM, UVM, etc.) including functional coverage and constrained random testing

4.Good knowledge of C, SystemC, and at least one of script languages: Perl, Python, etc.
5.Expert knowledge of VHDL/Verilog HDL and CAD tools (Synopsys and/or Cadence)
6.Team-work spirit, and with a strong drive to excel
7.Able to work independently on a given assignment and work hard to finish on time
8.Good written and communication skills
9.Previous experience on data network communication IC is an added advantage

IC Verification Engineer：

Responsibilities:
1.Compose the pre-silicon verification plan according to the chip specification and customer's use cases
2.Design Behavioral functional model and test-benches with C/System C. HDL and script languages
3.Create. build and implement test cases with high degree of accuracy to verify Device Under Test
4.Work closely with concept architect and RTL designer to verify RTL design through extensive testbench simulation for modular and top-level design to obtain very high percentage of functional and code coverage
5.Work closely with FPGA prototyping application and validation engineers to verify functional design
6.Coach the inexperienced interns in the team
7.Secondary task may include design of digital logic with high-level description language (VHDL/Verilog) from specification.

Requirements:

1,Master's/Bachelor's Degree in Electrical/Electronics or Computer Engineering.
2,Experience with verification methodologies including functional coverage and constrained random testing
3,Good knowledge of C, SystemC, and at least one of script languages: Perl, Python, etc.
4,Expert knowledge of VHDL/Verilog HDL and CAD tools (Synopsys and/or Cadence)
5,Team-work spirit, and with a strong drive to excel
6,Able to work independently on a given assignment and work hard to finish on time
7,Good written and communication skills
8,Previous experience in data communication network IC area is an added advantage

贵司有招聘需求的，欢迎和我联系；

如果你和你朋友有需要看工作机会的，发简历给我bestgrace@qq.com

Best Regards,

Grace Li

Principal Consultant & General Manager @ Hi-Talent Consulting Co. , Ltd.

上海芯相会企业管理咨询有限公司

E-Mail: bestgrace@qq.com

QQ: 710065861

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