PR Engneer（内部引荐）

jj_seu

Responsibilities:
1. Layout database creation : layout library and Milkyway database creation;
2. Initial floorplan : Initial chip or subchip level floorplan;
3. Place & Route: Perform cells placement; Perform global route and detail route;
4.  DRC/LVS corrections; Layout script creation: Create script to perform layout modification;
5. Create Apollo scheme file to maintain and update Apollo database;
6. Layout modification: Follow signal integration report to perform necessary modification;
7. Requirements: Bachelor Degree or higher in EE major;
8. 0-3 years P&R working experience;
9. Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我HR@Hi-Talent.net

Best Regards,
Apple
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
Mob:        15921265928
Skype:      ScarlettJaneJin
E-Mail:      Jane-Jin@Hi-Talent.net
QQ:         983144394
Blog:        http://blog.sina.com.cn/u/1716864892
Weibo:      http://weibo.com/u/1716864892
Linkedin:    jj_seu@hotmail.com

284294022

8. 0-3 years P&R working experience; 就是说应届生也可以？

jj_seu

Physical Design Technical Lead-
Role Information

Role
Physical Design Technical Lead
Role Designation
Technical Architecture

Purpose of the Role
Join the team responsible for the entire physical design flow (RTL to GDSII), as well as CAD & infrastructure development and research. The team utilizes the most advanced deep sub-micron technologies & constantly works on several tape outs/year
Educational Qualification and Experience Levels
Electrical Engineering or related discipline, Bachelor or above
2-8 Years working experience in semiconductor domain
Knowledge and Skills required for the Role
The candidate will perform Netlist to GDSII implementation of digital designs at the macro, core or top level.
Will be responsible for completion of tasks that may include full chip floor planning and partitioning, synthesis, formal verification, place and route, clock tree synthesis, power grid analysis, signal integrity analysis, timing closure and physical verification.
Good written and verbal communication skills

Areas of Responsibility

·         8+ years of experience in physical design
·         Must have experience with taping out chips using 40nm or below
·         Must have experience with the complete physical design flow using EDA tools Synopsys (PrimeTime, ICC is a must), Magma (Talus), Mentor Graphics (Caliber), and Cadence (First Encounter, Virtuoso, Conformal)
·         Some knowledge and some experience on process, parameters, synthesis, timing analysis, placement, routing, CTS, SI, power calculation, custom layout, timing analysis and DRC/LVS
·         Familiar with Verilog HDL, Spice
·         Good programming skill. Capable of writing Tcl or Perl

贵司有招聘需求的，欢迎和我联系；

如果你和你朋友有需要看工作机会的，发简历给我HR@Hi-Talent.net



Best Regards,

Apple

Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

上海芯相会企业管理咨询有限公司

Mob:        15921265928

Skype:      ScarlettJaneJin

E-Mail:      Jane-Jin@Hi-Talent.net

QQ:         983144394

Blog:        http://blog.sina.com.cn/u/1716864892

Weibo:      http://weibo.com/u/1716864892

Linkedin:    jj_seu@hotmail.com