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Cadence SH 招聘Principal/Lead PV Design Engineer
Ifyou have interest, PLS send your CV to zhangyl@cadence.com
Job Title:
Principal/LeadPV Design Engineer Job description: 1.
As an Encounter product validation engineer, he/she will contribute tooverall Encounter quality/stability and usability, enable designs easier tofinish design timing closure and chip finishing. 2.
Need to run different designs from placement/cts/optimization to finalSI timing closure, need to look at those timing degradations and analysis thereason, whether placement is not good, or optimization insert unreasonablebuffers, or routing pattern is detour, etc. Also need to analysis thosemax_tran/max_cap/DRC/power issues. 3.
Need to take new designs to add into regression suite. By given libraryand RTL netlist, she/he need to create floorplan, create powerplan, go throughAPR flow to achieve DRC clean and timing closure, to get reasonablePerformance/Power/Area metric, just like taping out designs. 4.
Can explore new flows or methodology to improve timing closureefficiency, and give customer support.
Positionrequirements: 1. Ph.D or excellent MS which is familiar with APR flow. 2. Good at STA. Know about place, routing, cts,optimization and SI analysis is a plus. 3. Know about RTL synthesis 4. Good at unix scripts, cshell. Perl is a plus 5. Strong ability in analysis and solving issues, strong ability infacing difficulty and challenges. Proactive in work. 6. Good English skill, communicationskill and good team work.
Cadence SH 招聘Principal/LeadPV Design Engineer
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