Cadence SH 招聘 PVS PE Mgr and Principal PVS PE

kengteng

Cadence SH 招聘 PVS PE Mgrand Principal PVS PE

If you have interest, PLS sendyour CV to zhangyl@cadence.com

Title:  PVS PE Manager

Position Description:

The Product Engineering teamworks with Customers and foundries, R&D, Marketing, and the FieldApplications Engineers to create products that address the unique and complexneeds of our customers. A Physical Verification Product Engineer managerprovides in-depth technical expertise and can lead a team in writing PhysicalVerification rule decks (i.e. DRC, ERC, FILL and LVS) and the usage of PhysicalVerification tools throughout physical implementation and signoff verificationcycles.

Responsibilities:

- Develop Physical Verificationrule decks (i.e. DRC, ERC, FILL and LVS)

- Setup efficient flows toimprove rule deck development quality and product performance

- Establish better process tolead team effort for efficient PVS rule deck development.

- Run expert-level benchmarksand solve complex customer problems.

- Work with the RD, field, customersand foundries to identify and define product requirement and enhancement

Position Requirements:         

Knowledge of developing ruledecks for commercial physical verification tools (e.g. PVS, Calibre, Hercules,Dracula, Assura, etc.) is required.

Experience in the followingareas:

- DRC, includes density,antenna, etc.

- LVS, includes deviceextraction, parameter measurement; connect/stamp sequences, short isolation,etc.

- Knowledge of netlist formatsSPICE, CDL, Verilog, etc.

- DFM, includes yield analysis,via insertion, OPC, FILL, etc.

Experience with layoutimplementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.) for thecreation of qualification cells is required.

Knowledge of automating testsuites for the qualification of rule decks is a plus.

Programming of Tcl, Perl, andSkill are a plus

EDUCATION: BS or MS inElectrical Engineering.

Titlerincipal PVS Product Engineer

Position Description:

The Product Engineering teamworks with Customers and foundries, R&D, Marketing, and the FieldApplications Engineers to create products that address the unique and complexneeds of our customers. A Physical Verification Product Engineer providesin-depth technical expertise in writing Physical Verification rule decks (i.e.DRC, ERC, FILL and LVS) and the usage of Physical Verification tools throughoutphysical implementation and signoff verification cycles.

Responsibilities:

Develop Physical Verificationrule decks (i.e. DRC, ERC, FILL and LVS)

Setup efficient flows toimprove rule deck development quality and product performance.

Run expert-level benchmarks andsolve complex customer problems.

Work with the RD, field,customers and foundries to identify and define product requirement andenhancement

Position Requirements:         

Knowledge of developing ruledecks for commercial physical verification tools (e.g. PVS, Calibre, Hercules,Dracula, Assura, etc.) is required.

Experience in the followingareas:

- DRC, includes density,antenna, etc.

- LVS, includes deviceextraction, parameter measurement, connect/stamp sequences, short isolation,etc.

- Knowledge of netlist formatsSPICE, CDL, Verilog, etc.

- DFM, includes yield analysis,via insertion, OPC, FILL, etc.

Experience with layoutimplementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.) for thecreation of qualification cells is required.

Knowledge of automating testsuites for the qualification of rule decks is a plus.

Programming of Tcl, Perl, andSkill are a plus

EDUCATION: BS or MS inElectrical Engineering.

sgwl87

请问，Principal PVS PE需要几年的rule deck 开放经验？