Cadence is looking for IC design, design services and verification Engineer

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Cadence is looking for IC design, designservices and verification Engineer

Ifyou have interest, PLS send your CV to zhangyl@cadence.com

SOC-R Physical Design Team

Positionead Physical Design Engineer

Location:Shanghai

Position Description:

-Performphysical design implementation, including synthesis, floor planning, power griddesign, place and route, clock tree synthesis, timing closure, power/signalintegrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFMClosure, and physical design project management.

-Thecandidate will have the opportunity to work on many varieties of challengingdesigns, i.e. low power and high speed design. The responsibility includesparticipating in or leading next generation physical design, methodology andflow development.

                                                         

Position Requirements:         

1.BSdegree with 10+ years of applicable experience, MS degree with 7+ years ofapplicable experience in electrical engineering, microelectronics.

2.Experiencedwith ASIC design flow, hierarchical physical design strategies, methodologiesand understand deep sub-micron technology issues.

3.Solidknowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalkanalysis, formal verification, physical verification, DFM.

4.Successfultrack records of taping out complex, 65/40/28 nm SOC chips.

5.Automationand programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.

6.Self-motivated, able to work independently or as a team player, excellent verbaland written communication skills in English.

SOC-R Design Services Team

Positionead Implementation Services Engineer

Location:Shanghai

Position Description:

1.Thecandidates should be senior in a way that they are not only technical excellentbut also mature & able to communicate with customers, following teammembers.

2.Thisengineer should have excellent design experiences in the digital implementationdomain including Floorplan, P&R, STA, Physical verification, DFM.

3.Theengineer must have a solid background in circuits, electronics & physics& should be very willing to learn new stuff.

Key Accountabilities:

1.Abilityto handle large sized design implementation tasks & architectural tasksalone. 2.Ability to assess Customer's Design environment, to understand hisapplication needs & to build new Design environment based on specifications& available Cadence tool technology.

3.Abilityto acquire a basic understanding of the (services) business environment ofCadence within 1 month.

4.Workingon multi person projects of varying complexity, working especially in a multi-site/multi-culturalproject. The latter requires good communication skills in English. 5.Feelingresponsible for technical delivery as well as business development &opportunity creation. Behavioral competencies: Teamwork; Customer focus; 6.Accountability;Communication; Coaching & feedback; Employee development; Leadership.

                                                         

Position Requirements:         

1.BSdegree with 10+ years of applicable experience, MS degree with 7+ years ofapplicable experience in electrical engineering, microelectronics.

2.Essentialthat the individual demonstrates strong communication, verbal and written, andproject management skills.

3.Requiresgood communication skills in English.

Ifyou have interest, PLS send your CV to zhangyl@cadence.com

SOC-R Front-end Design Team

Principal Verification Engineer

Location: Shanghai/Beijing

Position description:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Specific dutiesinclude:

--Deep understanding on ASIC/SOC design flow

--Excellent knowledge of advanced verificationmethodology like eRM/OVM/UVM

–Familiar withCadence’s Incisive Plan to Closure Methodology (IPCM)

--Proficiency inSystem Verilog,  System C and/or e (Specman)

–Developing and usingVerification Components (eVC, OVC, UVC, VIP)
–Developing and using assertion basedverification and formal analysis methods

--Skilled inscripting language, such as Perl, C shell, Makefile
–Assessing the project verification requirements
–Operating in a lead role regardingarchitecting and implementation of project verification environment/solution.

–May coordinate/leadothers within the scope of a defined project

EssentialQualifications:

-Musthave BS degree with 10+ years of applicable experience, MS degree with 7+ yearsof applicable experience in electrical engineering, microelectronics,comparable engineering science or solid state physics.

-Essentialthat the individual demonstrates strong communication, verbal and written.Requires good communication skills in English.

DesirableQualifications:

A minimum of seven years relevant experience in industry.

-Will have demonstrated hands-on experience and expertise with Cadence verificationdesign tools or equivalent tools, flows and methodologies required to execute averification project.

-Will have demonstrated successful completion of 10+ verification projects as anindividual contributor

-Will have ARM based SoC designs at system project verification experience