知名企业招聘IC设计和验证工程师(成都)

haha981604

以下是研发部招聘的职位,有兴趣的兄弟姐妹可以来凑凑热闹....

1. Digital IC Design Engineer
JOB DESCRIPTION:
- Micro-architecture definition/writing IC design spec.
- RTL coding for logic modules.
- Simulation/Verification of functionalities at both module level and top level.
- Do module level synthesis / timing analysis
- Writing complete design/verification reports
- Silicon debug of the related module functionalities
- Writing test patterns for production tests

QUALIFICATION:
- BSEE with minimum 1 year or MSEE with minimum 1 year experience of digital design experience
- Experience on SERDES is preferred.
- Relevant experience in high-speed digital design (Semi-flow: customer layout + ASIC flow) is must
- Relevant experience in Cadence ICMS/ICFB design environment is must
- Solid knowledge of digital design building blocks (eg. Data-path, Synchronizer, FIFO...)
- Strong skills of Verilog RTL coding and verification and debug.
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Relevant experience in DDR/PCIE/USB/ETH interface design is a plus
- Self-motivated and team player


2. System Verification Engineer
JOB DESCRIPTION:

- Build system functional model based on technical specification or product description and requirement with system verilog or systemC.
- Make test plan and write testbench to verify functionality and performance of ASICS.
- Develop/maintain/enhance environment tools/scripts/make files.

QUALIFICATION:
- BSEE with minimum 1-year experience in ASIC verification.
- Good knowledge on (systemverilog or systemc) and verilog.
- Hands on experience with simulation and verification tools, such as NC, Questasim/VCS.
- Proficiency in one of Specman E/Vera/SystemVerilog/SystemC verification tools.
- Strong teamwork and communication ability.



以上职位工作地点均为: 成都市高新区
有意者可将您个人简历及应聘职位发送到邮箱: haha981604@163.com (这里就不用公司的邮箱了,避免麻烦...)
至于大家感兴趣的高薪到底有多高,这就要根据您的能力来定了(可以透露的是月薪+JJ+FH)

huanguestc002

回复 1# haha981604

硕士应届可以不？

zhuyujun

成都市高新区

wuyin_gj

基本状况已经写道你的邮箱中， 请查看。