【社会招聘】LSI上海研发中心2012年1月最新职位

yulingyanyuyu

新年好！2012 LSI上海研发中心的扩张脚步依然继续。。。欢迎有志于芯片研发的您加入！！！

有意者，请将简历发至：Tracey.zheng@lsi.com

如有任何疑问，请发送邮件至Tracey.zheng@lsi.com或拨打电话021-24191709.

也可加我msn: zql975504@hotmail.com

或者微博啊：http://www.weibo.com/u/1752448637

LSI上海研发中心位于徐汇区中山南二路徐汇苑大厦（8万人体育场对面）

1.
Software Quality Assurance(SQA)

Education and Experience Requirements

BS in Electrical Engineering, Computer Science, or Computer Engineering is required with 6+ years of firmware development.

M.S. preferred with 4+ years in software / hardware validation

Knowledge, Skills, and Abilities

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Quick learner with high level of self-motivation and dedication, with ability to deliver high quality products on time

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Meticulous, methodical, uncompromising, and creative in testing

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Experience in software debugging, problem creation and trapping

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Experience in devising testing / validation methodology is strong plus

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Communicate effectively in a team, able to multitask effectively in fast-paced environment.

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Understanding of NAND Flash concepts, knowledge of Flash management techniques, including wear leveling, garbage collection (strong plus).

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Knowledge and hands-on experience with storage protocols is preferred (SAS / SATA)

2.
Firmware Engineer

Education and Experience Requirements

BS in Electrical Engineering, Computer Science, or Computer Engineering is required with 6+ years of firmware development.

M.S. preferred with 4+ years in firmware development.

Knowledge, Skills, and Abilities

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Must demonstrate expertise in design and implementation of event-driven, real time firmware solutions using C/C++ programming

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Must be able to work with ASIC and software engineers in a collaborative environment

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Quick learner with high level of self-motivation and dedication, with ability to deliver high quality products on time

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Must have an excellent computer science background and demonstrated strength in designing efficient embedded firmware for storage or networking products

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Firmware/System debug skills utilizing debugger, protocol analyzer is required

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Good understanding of RTOS concepts including task switching, deadlocks, and resource management issues is required

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High level of skill in problem recreation, trapping and resolution, possess good written and verbal communication skills.

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Communicate effectively in a team, able to multitask effectively in fast-paced environment.

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Understanding of NAND Flash concepts, knowledge of Flash management techniques, including wear leveling, garbage collection (optional but strong plus).

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Knowledge and hands-on experience with storage protocols is preferred (SAS / SATA)

3.
Read Channel Verification Engineer

JOB DESCRIPTION:

As a member of the Read Channel team, candidate must be willing to work as an extended

member of the design team. Duties will include functional verification of Storage read

channel mixed-signal IP. Candidate will be expected to contribute to design and development

of System Verilog based verification environment and will be responsible for verification

closure of block/chip/system level functions for mixed signal based IP. Experience with

System Verilog and functional coverage methodologies are required. Must be willing to

follow a disciplined verification methodology and to work closely with a multi-location,

international design team. Excellent teamwork and communication skills are required.

PREFERRED EXPERIENCE:

BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.

Required knowledge and skills:

- Expertise in System Verilog required

- Good understanding of Digital Signal Processing

- Good understanding of Analog and Digital Circuits

- Very good analytical/debugging skill

- Good verbal and written communication skills

Desirable skills:

- Knowledge of Verilog-AMS, Perl

- Knowledge of verification methodologies including functional coverage and constrained

random testing

- Knowledge of VLSI design flows & DFT

- Familiarity of high level programming language

- Experience working with globally distributed team

4.
Digital Design Engineer-Shanghai

Job Responsibilities

Working with an Architecture/Algorithm Development Team to finalize system architecture

for optimal implementation of digital signal processing algorithms, including architectural

definition and tradeoffs, die size, power estimation.

Skill required:

Digital logic design, verilog coding, logic synthesis, both RTL and gate level verification,

formal verification and static timing analysis. Unix shell, Perl scripting, C/RTL co-simulation.

Sound theory background  of communication and Digital signal processing.

5.
ASIC Customer Engineer-Shanghai

Job Description

- LSI Corporation offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing LSI's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 40nm/28nm designs.

Requirements/Qualifications (Education)

Education: BS/MS Electrical, Computer Engineering or Equivalent

- Candidates have ONE OR MORE good skill sets of the following areas are highly encouraged to apply:

- RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of design

- implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for complex ASIC

- environments. This would include strategies for power management.

- OR

Physical Design Implementation: The ideal candidate should be strong in the Physical Design (at least at block level) which includes floor planning, design closure, & STA. Having strong DRC & LVS skills are a plus.

- Synopsys Astro/ICC experience a plus. Having Mentor Calibre skills a plus.

- OR

- Physical Verification: The ideal candidate should have in-depth understanding of transistor level IC fabrication process, familiar with major foundries(TSMC or SMIC) runsets and verification flow, custom layout experience is a plus, successfully done LVS/DRC/ERC/Antenna check for multiple tapeouts is a strong plus. Understanding of DFM is a plus. Calibre experience is a plus.

- OR

- DFT: The ideal candidate should be strong in all DFT (Design for Test) for all aspects. This would include
- scan/TDF, TestKompress, MEMBIST/BISR, JTAG and etc. Having STA skills is a plus for all aspects of test. Responsible for support / debug of customer designs after delivery of prototypes

6.
SerDes Application Engineer

JOB DESCRIPTION:

Applications engineer for custom silicon integrated circuits with SerDes interfaces located in

Shanghai, China. Work as part of a team of highly skilled applications engineers located in

Milpitas, CA, and Allentown, PA, along with local field applications and sales engineers. The

successful candidate will work directly with the customer supporting custom silicon IC’s with

responsibilities including product definition, SerDes integration, channel definition and analysis,

system bring up, and production ramp. This individual must be highly motivated and capable of

working independently or as part of a team. Expertise in high speed serial interfaces and PCB

signal integrity is required.

PREFERRED EXPERIENCE:

- Oral and written communication skills in both Chinese and English

- Microsoft Office Tools including Excel, Powerpoint, and Word

- Detailed understanding of serial communications

- Knowledge of serial communications standards including XAUI, SRIO, OIF-CEI,

IEEE802.3ap, Fibre Channel, SFF-8431

- Knowledge of semiconductor technology

- Desired: Use of state of the art test equipment including sampling scopes, BERTs, real

time scopes. High speed PCB layout design techniques and modeling

Education/Certifications

BSEE plus 8 years relevant experience in semiconductors with serial interfaces or

MSEE plus 5 years relevant experience in semiconductors with serial interfaces

7.

Signal Integrity & Application Engineer

JOB DESCRIPTION:

This position will define SI requirements on advanced memory interface solutions including

DDR3/4, RLDRAM III and ONFI 2.2 NAND Flash interfaces. Work in a co-design environment

by providing specifications to IO and package designers. Develop IP implementation

guidelines based on feasibility analysis and support internal design teams. Provide complete

application support to customers by providing SI Kits, Timing Budgets and System Design

Application Notes.

PREFERRED EXPERIENCE:

- Education Requirements: MSEE with 5 or BSEE with 7 years experience in high speed

interface design and signal integrity.

- Hands on experience with high speed interfaces (DDR1/2/3, RLDAM II, QDR SRAM,

Flash, USB) implementation and hardware system experience is a must..

- Experience in Serial Interface architecture, protocols, Backplane design/analysis is

preferable.

- System Signal Integrity analysis experience with HSPICE is must and familiarity with tools

such as Agilent ADS, Sigrity Power-SI, Ansoft HFSS, Apache tools.

- Knowledge of IBIS modeling, board & package model extraction, via modeling.

- Proficiency in Electromagnetic, Transmission-line & S-parameters theory and modeling.

- Understanding of signal integrity analysis parameters and evaluate trade-offs between

design parameters to determine an optimum solution space.

- Simulating and analyzing Power distribution network.

- Firmware knowledge and programming skills in Excel, PERL, Verilog and Matlab is

preferred.

- Experience using lab measurement tools such as oscilloscopes, TDR, VNA and software

tools such as Labview, PLTS.

- Strong written and oral communication in Chinese and English with customer service skills

8.
Field Coreware Engineer

JOB DESCRIPTION:

This position will support DDR/DDR2/DDR3, QDR, RLDRAM, and/or NAND Flash memory

Interface IP applications and their future versions. Customer interface. Generate application

notes. Work with development teams to provide customer technical support. Memory Interface

Phy IP customization.

PREFERRED EXPERIENCE:

- Verilog RTL coding, logic simulation, Synsopsys Design Compiler, Synopsys PrimeTime

STA, Good communication skill, Technical writing (Tech Manual, App Notes, Datasheet)

- BSEE or equivalent, and 3 years logic design industrial experiences, preferrable in

DDR/DDR2/DDR3 SDRAM, QDR SRAM, RLDRAM, and/or NAND Flash memory

Interface

9.
Field Application Engineer-SSD Processor -Shenzhen

Job Description

- Responsible for China local FCD SSD Processor technical support

- Responsible for China local Disty FAE training

Requirements/Qualifications (Education)

- Minimum 5 years engineering experience

- FAE/AE working background preferred

- BS degree and above require in EE or related

- Good communication in English

10.
Product Engineer

Job Description

To support new product release and manage product characterization for eventual robust production release

Drive yield improvement activities at both wafer sort and final test areas and work in conjunction with foundries to reduce product defectivity

Manage product costs and drive for cost reduction initiatives
Deploy yield engineering tools for analysis and drive for corrective actions
Analyze product return from customers to improve test coverage and reduce product dppm

Requirements/Qualifications (Education)

University graduates with 2 years or more semiconductor product or testing experiences
- Solid background in high speed digital and mixed-signal testing is essential
- Working experiences with ATE. Credence Quartet or HP93K or Teradyne Catalyst will be of advantage
- C++ and/or Perl programming skills

11.
Test Engineer

Job Description

To support prototype and production releases of new products. Manage debug of test program, design and debug of test hardware, and meet product release schedule.

Support test program development for implementing changes in new test methodologies for test coverage improvement.


Pursue Design for Test initiatives to optimize testability and achieve test cost reduction via test time reduction and multiple site test solutions for production release.


Support test chip test development and characterization of new IP used in LSI products.

Requirements/Qualifications (Education)

University graduate students with top scores in GPA

Prior working experiences in the semiconductor industry field, specially in either IDM, Fabless, or Foundry environment

ATE programming skills would be essential

C++ and/or Perl programming skills