【招聘】LSI上海研发中心诚招ASIC Customer Engineer

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LSI公司简介-上海研发中心位于徐汇区徐汇苑大厦，深圳办公室位于帝国大厦
LSI公司成立于1981年，总部设在美国硅谷。LSI在全球拥有5000多名员工，在20几个国家和地区设有分公司，在中国拥有上海、北京、深圳、香港、台湾等分支机构。拥有强大的产品研发、销售、市场、技术服务队伍。LSI公司是创新芯片、系统和软件技术的领先供应商，采用LSI技术的产品可以使消费者与信息及数码内容之间无缝的融合。
公司在众多领域提供产品和服务，包括定制标准芯片、适配器、系统和软件。我们的产品已经获得众多世界级知名品牌的信任，为存储和网络市场提供了许多领先的解决方案。
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1.
ASIC Customer Engineer-Shanghai
The Customer Design Engineer is a challenging and cutting-edge position working with LSI
internal methodology and foundation IP development teams to support complex ASIC designs
for either external tier one customers or internal ASSP programs.
As an integral member of the customer design engineering team, the ASIC Customer Engineer
has responsibility for a wide range of tasks, including chip floor planning, place and route,
timing analysis, signal integrity, test, and design verification.
Responsible for support and completion of designs from customer provided RTL or Gate level
netlist using the latest LSI technologies.
Design completion tasks include
- Presales Support (die size support, memory generation, address customer questions and
concerns.)
- RTL Analysis & Synthesis
- Physical Design Implementation (bonding, floor planning, power structure insertion, place
and route, timing closure) using Synopsys Astro or ICC tools
- Test insertion using Mentor, LogicVision, or Virage tools
- Formal Verification (Verplex or Formality)
- Static Timing Analysis (Primetime and Primetime SI)
- Cross talk analysis
- Power verification
- DRC & LVS
Overtime, all ASIC customer engineers within the design center are expected to develop the
skills to be able to do most of the tasks described above in this role. Candidates having strong
skill sets one or more of the following areas should apply:
RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of
design implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for
complex ASIC environments. This would include strategies for power management.
or
Physical Design Implementation: The ideal candidate should be strong in either the Physical
Design which includes floor planning, design closure, & STA. Having strong DRC & LVS skills
are a plus. Strong Synopsys Astro/ICC experience a plus. Having strong Mentor Calibre skills
a plus.
or
PREFERRED EXPERIENCE:
5+ years experience in ASIC design and implementation. Familiar with Verilog RTL coding,
Verilog Simulators (NC or VCS) , Synopsys Design Compiler, Synopsys ICC Physical design
tools, PrimeTime for Static Timing Analysis, Mentor FastScan, LogicVision, Verplex (or
Formality), and scripting. The ideal candidate should have completed at least one successful
ASIC or ASSP tapeout. Successful tape out using Synopsys Astro or ICC considered a strong
plus. Experience in working with customers desired. Experience in working with and
debugging prototypes considered a strong plus. Knowledge and hands on use of test insertion
/ vector generation / verification a plus. Some experience with Signal integrity a bonus. Must
possess excellent communication skills; be able to effectively communicate with other
members of the design team, supporting organizations, and management.
Education/Certifications
BS/MS Electrical, Computer Engineering or Equivalent.