2_1_slides_final[MedPart A Multi-Level Evolutionary Differentiable Hypergraph Partitioner].pdf
2_2_slides_final[FuILT Full Chip ILT System With Boundary Healing].pdf
2_3_slides_final[Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops].pdf
3_1_slides_final[Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement].pdf
3_2_slides_final[Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack Dependency].pdf
3_3_slides_final[Parallel and Heterogeneous Timing Analysis Partition, Algorithm, and System].pdf
4_1_slides_final[EDA Needs at Advanced Technology Nodes].pdf
4_2_slides_final[EDA Challenges at Advanced Technology Nodes].pdf
4_3_slides_final[Challenges in Floorplanning and Macro Placement for Modern SoCs].pdf
5_1_slides_final[Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs].pdf
5_2_slides_final[Unified 3D-IC Multi-Chiplet System Design Solution].pdf
5_3_slides_final[Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects].pdf
5_4_slides_final[Enabling System Design in 3D Integration Technologies and Methodologies].pdf
6_1_slides_final[FastTuner Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning].pdf
6_2_slides_final[Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model].pdf
6_3_slides_final[AI for EDAPhysical Design].pdf
6_4_slides_final[DSO.ai – A distributed system to optimize design flows].pdf
6_5_slides_final[Solvers, Engines, Tools and Flows The Next Wave for AIML in Physical Design].pdf
7_1_slides_final[Physical Design Challenges in Modern Heterogeneous Integratio].pdf
8_1_slides_final[Fundamental Differences Between Analog and Digital Design Problems].pdf
8_2_slides_final[Layout Verification Using Open-Source Software].pdf
8_3_slides_final[Reinforcement Learning or Simulated Annealing for Analog Placement A Study based on Bounded-Sliceline Grids].pdf 9_1_slides_final[Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment Constraint].pdf
9_2_slides_final[Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells].pdf
9_3_slides_final[IncreMacro Incremental Macro Placement Refinement].pdf
9_4_slides_final[Timing-Driven Analytical Placement According to Expected Cell Distribution Range].pdf
10_1_slides_final[Routability Booster–Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources].pdf
10_2_slides_final[Novel Transformer Model Based Clustering Method for Standard Cell Design Automation].pdf
10_3_slides_final[Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization].pdf 11_1_slides_final[Introduction of 3D IC Thermal Analysis Flow].pdf
11_2_slides_final[3Dblox Unleashing The Ultimate 3DIC Design Productivity].pdf
11_3_slides_final[Challenges for Automating PCB Layout].pdf
12_1_slides_final[Scheduling and Physical Design].pdf
12_2_slides_final[Accelerating EDA from 1 to N].pdf
12_3_slides_final[Pioneering Contributions of Professor Martin D. F. Wong].pdf
12_4_slides_final[My Journey in EDA].pdf
13_1_slides_final[Computing Architecture for Large Language Models (LLMs) and Large Multimodal Models (LMMs)].pdf
14_1_slides_final[SMT-Based Layout Synthesis].pdf
14_2_slides_final[Qubit Mapping for Trapped-Ion Systems Using].pdf
14_3_slides_final[Optimization for Buffer and Splitter Insertion in].pdf
15_1_slides_final[Design Automation Challenges for Automotive Systems].pdf
15_3_slides_final[Solving the Physical Challenges for the Next Generation of].pdf
16_1_slides_final[ISPD'24 Contest GPUML-Enhanced Large Scale Global Routing Contest].pdf
16_2_slides_final[Closing Remarks].pdf
