标题: XA+VCS addr4仿真 出现“Module or design unit `addr4' specified in ..."ERROR [打印本页] 作者: zh17863817115 时间: 2024-7-2 11:06 标题: XA+VCS addr4仿真 出现“Module or design unit `addr4' specified in ..."ERROR 请问各位大佬，我照着网上数模混合仿真实例（数字verilog作为顶层）VCS+Xa - 知乎 (zhihu.com)的教程，一直报错，是什么原因呢？
Error-[MSV-SETUP-IUC] Invalid use clause
vcsAD.init, 2
"addr4"
Module or design unit `addr4' specified in the use_spice clause in the Mixed
Signal setup file cannot be found in the Spice library.