A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
Published in: 2022 IEEE International Solid-State Circuits Conference (ISSCC)
Date of Conference: 20-26 February 2022
Date Added to IEEE Xplore: 17 March 2022
DOI: 10.1109/ISSCC42614.2022.9731537
Publisher: IEEE
Conference Location: San Francisco, CA, USA
文章链接： https://ieeexplore.ieee.org/document/9731537 作者: lingfengqing5 时间: 2024-10-7 16:48
跟楼主一样，同求作者: Vawell 时间: 2024-10-7 19:11 ( , 下载次数:
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