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标题: 施密特 [打印本页]
作者: wyjly 时间: 2024-2-22 19:06
标题: 施密特
各位佬下图施密特输出级和非门之间为什么要加两个PMOS 他的作用是啥欸
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作者: wyjly 时间: 2024-2-22 19:34
非门前面的两个PMOS是啥作用欸
作者: jw8704 时间: 2024-2-22 20:00
Please refer as bwlow site.
https://industrial-electronics.c ... -com/esd-c-d_7.html
9. BIPOLAR TRANSISTOR RECEIVERS
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FIG. 20 Modified Schmitt trigger network for ESD improvement 9.1 Bipolar Single Ended Receiver Circuits
Receiver circuits are a common ESD sensitive circuit in Bipolar and BiCMOS technology.
Bipolar receiver circuits typically consist of npn bipolar transistor configured in a common emitter configuration (FIG. 21). For bipolar receivers, the input pad is electrically connected to the base contact of the npn transistor, with the collector connected to VCC either directly or through additional circuitry. The npn bipolar transistor emitter is electrically connected to VSS, or through a emitter resistor element, or additional circuitry.
In bipolar receiver networks, for a positive-polarity HBM ESD events, as the base voltage increases, the base-to-emitter voltage increases leading to forward biasing of the base- emitter junction. The base-emitter junction becomes forward active, leading to current flowing from the base to the emitter region. Typically in bipolar receiver networks, the physical size of the emitter regions are small. When the ESD current exceeds the safe operation area (SOA), degradation effects occur in the bipolar transistor. The bipolar device degradation is observed as a change in the transconductance of the bipolar transistor. From the electrical parametrics, the unity current gain cutoff frequency, fT, decreases with increased ESD current levels. From a fT-IC plot, the fT magnitude decreases with ESD pulse events, leading to a decrease in the peak fT.
For a negative pulse event, the base-emitter region is reverse biased. As the voltage on the signal pad decreases, the base-emitter reverse-bias voltage across the base-emitter metallurgical junction increases. Avalanche breakdown occurs in the emitter-base metallurgical junction, leading to an increase in the current flowing through the emitter and base regions; this leads to thermal runaway and bipolar second breakdown in the bipolar transistor. The experimental results show that the negative-polarity failure level has a lower magnitude compared to the positive-polarity failure level.
One common ESD design solution used to provide improved ESD results in a single ended bipolar receiver network is to place a p-n diode element in parallel with the npn bipolar transistor emitter-base junction (FIG. 22). Using a parallel element, the p-n junction is placed such that the anode is electrically connected to the npn emitter, and the cathode is electrically connected to the npn base region; this ESD element serves as a bypass element avoiding avalanche breakdown of the npn base-emitter junction. The diode element is placed local to the npn transistor element to avoid substrate resistance from preventing early turn-on of the ESD diode element. Note that this element is analogous to the CDM solution used in CMOS receiver networks. For a bipolar transistor, it is serving for events from both the signal pad and potential events from the emitter electrode.
In radio frequency (RF) bipolar receivers, metal-insulator-metal (MIM) capacitors are used between the signal pad and the base electrode. For positive- or negative-mode polarity events, the MIM capacitor can fail due to dielectric degradation. Without ESD protection on the receiver network, the ESD failure levels of the receiver network will be limited by the MIM capacitor element. An ESD solution to prevent ESD failure in these RF bipolar receivers is to use a p-n diode element in parallel with the MIM capacitor element. The p-n diode element can be in a reverse configuration so that it serves as a parallel capacitor element, and does not allow a dc voltage to be transmitted between the signal pad and the bipolar receiver base element. The functional disadvantage of the p-n element is the impact of the effective quality factor ''Q'' of the capacitor element.
作者: tracy6969 时间: 2024-2-23 04:06
interesting
作者: castrader 时间: 2024-2-23 08:41
但是那两个多的MOS其gate分别直接接电地...这是ESD上的找死行为吧...
作者: younng 时间: 2024-2-23 09:24
我看着上面那个是NMOS呀，名字叫n19
作者: castrader 时间: 2024-2-23 09:28
我就是这个意思啊
N19的gate直接接在VDD上，就不怕VDD的ESD穿了它？
作者: younng 时间: 2024-2-23 09:39
本帖最后由 younng 于 2024-2-23 09:57 编辑
其实我是么有看懂他为什么是ESD 的，电源进来的时候已经经过ESD的了。这个vdd不会被击穿，如果他会被击穿那么所有都要加esd电源esd不就没用了。盲猜一下那里加个电阻形成寄生电容电感增加了电路EMC
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