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标题: 12bit的SAR ADC一般可以做到多少速率? [打印本页]

作者: 花花233    时间: 2022-4-24 16:31
标题: 12bit的SAR ADC一般可以做到多少速率?
小弟之前做过一个12位的SAR ADC,最高采样率1M。
现在想改成一个5M左右的,用SAR结构可以实现吗?
原来的设计把时钟调快之后仿真发现有效位数比较低,3M时前仿有效位数只有11左右了。想问问哪些因素会限制SAR ADC的速率,可以做哪些修改来提高采样率?
作者: wkp1992101    时间: 2022-4-24 17:07
增加采样阶段的时间,增大输入信号的驱动能力,增加比较器的响应速度,降低采样电容等均可提高采样率
作者: flscut    时间: 2022-4-24 17:11
最高可以5MHz, T40/T55
作者: 花花233    时间: 2022-4-24 19:49


   
flscut 发表于 2022-4-24 17:11
最高可以5MHz, T40/T55


请问T40/T55是什么意思?

作者: IcRabia    时间: 2022-4-25 09:02
请问12b 1M有推荐的架构吗

作者: andy2000a    时间: 2022-4-25 09:13


   
花花233 发表于 2022-4-24 19:49
请问T40/T55是什么意思?


I think maybe tsmc  40nm  55nm  ??




作者: frj8848    时间: 2022-4-25 09:42
Designware在40nm下有160M 12bit的产品IP
作者: castrader    时间: 2022-4-25 10:04
160M 12b这个一般是通讯意义上的SARADC,在量程、增益等方面与普通的1M左右的SAR ADC定义不太一致。

作者: 敬山一休    时间: 2022-4-25 10:15


   
花花233 发表于 2022-4-24 19:49
请问T40/T55是什么意思?


tsmc 40nm 和55nm

作者: 花花233    时间: 2022-4-25 16:32
如果单位电容取20f,最高位电容2.56p,开关导通电阻大概是50欧,那时间常数算出来128ps,可以认为电容阵列每次切换需要400ps就基本可以稳定吗?
作者: peterlin2010    时间: 2022-4-25 17:27


   
castrader 发表于 2022-4-25 10:04
160M 12b这个一般是通讯意义上的SARADC,在量程、增益等方面与普通的1M左右的SAR ADC定义不太一致。
...


A 40-nm CMOS 12b 120-MS/s Nonbinary. SAR  


200M  pipelined-SAR ADC

40nm CMOS 12b 200MS/s Single-amplifier Dual ...


A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

https://bbs.eetop.cn/thread-614241-1-1.html




作者: sunjimmy    时间: 2022-5-2 14:56
2021_An 18.39 fJ-Conversion-Step 1-MSPS 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC


作者: sunjimmy    时间: 2022-5-2 15:00
2014_An analog front end with a 12-bit 3.2-MS_s SAR ADC for a power line communication system


作者: sunjimmy    时间: 2022-5-3 14:37
2017_A 12-14 bit 4-2MSPS SAR ADC in 65nm Using Novel Residue Boosting_CICC17


作者: sunjimmy    时间: 2022-5-4 15:54
Chip design of a 12-bit 5MS/s fully differential SAR ADC with resistor-capacitor array DAC technique for wireless application

Published in: 2015 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

Abstract:
A 1.8-V 12-bit 5MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. To reduce DAC switching energy and chip area, a hybrid resistor-capacitor DAC is applied. To save energy, asynchronous control logic to drive the ADC is used. A pre-amplifier based comparator circuit is built to reduce the kickback noise from the dynamic latch designs. With 1.8 V supply voltage and 5.0 MHz sampling rate, measured results achieve -0.55/0.72 LSB (Least Significant Bit) of DNL (differential nonlinearity) and -0.78/0.92 LSB of integral nonlinearity (INL) respectively, and 10.76 bits of an effective number of bits (ENOB) at 1MHz input frequency. The chip area is 0.83 mm 2 including pads and the power consumption is 490μW for optical and wireless communications.
作者: sunjimmy    时间: 2022-5-4 15:55
12-Bit 5 MS/s SAR ADC with Hybrid Type DAC for BLE Applications

Published in: 2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN)

Abstract:
This paper presents a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) designed for a Bluetooth Low Energy (BLE) application. The objective of this work is to reduce the number of capacitors in the Capacitor Digital to Analog Converter (CDAC). To achieve this, a hybrid type DAC has been applied where 8 Most Significant Bits (MSB)s are decided through capacitive DAC and 4 Least Significant Bits (LSB)s are decided in a Resistor DAC (RDAC). The conversion speed for this design reaches up to 6 MS/s. The prototype ADC is designed in a 90 nm complementary metal-oxide semiconductor (CMOS) process. The analog and digital supply voltage range for this design are 2.7-5.5 V and 1.1-1.3 V respectively. For 6 MS/s conversion rate, this ADC achieves up to 11.8 and 11.2 effective number of bits (ENOBs), for maximum and minimum supply voltages respectively. The current consumption from a 5 V supply voltage is 980 µA and the Figure of Merit (FOM) is 229 fJ/Conv.step.
作者: sunjimmy    时间: 2022-5-4 16:00
2021_12-Bit 5 MS/s SAR ADC with Hybrid Type DAC for BLE Applications



作者: sunjimmy    时间: 2022-5-4 16:20
A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS

Published on Apr 1, 2018 in International Journal of Circuit Theory and Applications

Summary
This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious-free dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-to-noise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step.
作者: maverick28229    时间: 2022-5-10 01:13
thanks for sharing infor.
作者: 骷髅书生    时间: 2022-5-10 09:39
mark~
作者: zhanweisu33    时间: 2023-11-9 14:38
追求高速的话,单通道pipeline-sar到800Msps左右也不少了
作者: chinapr    时间: 2023-11-21 19:12
谢谢分享哟
作者: irwinluo    时间: 2024-12-4 16:47

谢谢分享




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