lunatic_wei@PC-20201004MJRO:/opt/sim/20220210$ vcs -R +v2k r2.v r1.v -timescale=1ns/1ns -debug_acc+fsdb -o simv
*** Using c compiler gcc-4.8 instead of cc ...
Chronologic VCS (TM)
Version O-2018.09-1_Full64 -- Fri Feb 11 15:02:22 2022
Copyright (c) 1991-2018 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
15:02:22 (snpslmd) OUT: "VCSCompiler_Net" lunatic_wei@PC-20201004MJRO [snps_checkout_1644562942]
Parsing design file 'r2.v'
Parsing design file 'r1.v'
Top Level Modules:
testbench
TimeScale is 1 ns / 1 ns
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module testbench
15:02:23 (snpslmd) IN: "VCSCompiler_Net" lunatic_wei@PC-20201004MJRO [snps_checkout_1644562942]
15:02:23 (snpslmd) OUT: "VCSCompiler_Net" lunatic_wei@PC-20201004MJRO [snps_checkout_1644562943]
15:02:23 (snpslmd) IN: "VCSCompiler_Net" lunatic_wei@PC-20201004MJRO [snps_checkout_1644562943]
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld: archive.0/_21502_archive_1.a(iAVhC_d.o): .symtab local symbol at index 33 (>= sh_info of 3)
ld: archive.0/_21502_archive_1.a(iAVhC_d.o): error adding symbols: bad value
make[1]: *** [filelist.cu:7: _21502_archive_1.so] Error 1
make: *** [Makefile:103: product_clean_order] Error 2
Make exited with status 2
CPU time: .734 seconds to compile + .297 seconds to elab + .391 seconds to link
Warning: [DVIT101]
Rename of DVE log directory failed: Permission denied.
From path: '/opt/sim/20220210/DVEfiles'.
To path: '/opt/sim/20220210/.saveDVEfiles'.
Please ensure you have write permission in the directory.
*** Using c compiler gcc-4.8 instead of cc ...
Chronologic VCS (TM)
Version O-2018.09-1_Full64 -- Fri Feb 11 15:52:11 2022
Copyright (c) 1991-2018 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'r1.v'
Parsing design file 'r2.v'
Top Level Modules:
r2
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld: archive.9/_25962_archive_1.a(amcQwB.o): .symtab local symbol at index 30 (>= sh_info of 2)
ld: archive.9/_25962_archive_1.a(amcQwB.o): error adding symbols: bad value
make[1]: *** [filelist.cu:7: _25962_archive_1.so] Error 1
make: *** [Makefile:103: product_clean_order] Error 2
Make exited with status 2
CPU time: .610 seconds to compile + .297 seconds to elab + .173 seconds to link
Error: [DVIT009]
Build error for command 'vcs -full64 -cpp g++-4.8 -cc gcc-4.8 -LDFLAGS -Wl,--no-as-needed -R +v2k r1.v r2.v '.
Build directory '/opt/sim/20220210'.
/opt/sim/20220210/r2.v: line 1: syntax error near unexpected token `('
/opt/sim/20220210/r2.v: line 1: `module r2();'
Error: [UCLI-020] Tool initialization error
Internal error with tool initialization. File "/opt/sim/20220210/r2.v" failed to startup properly
If problem persists, please report this error to a Synopsys representative.