没有PMOS驱动就没有泄放回路，同时NMOS是有一定电流驱动能力的，NMOS的输出端电压会不断升高，直到VDD；另外LDO是有泄放回路的作者: jiang_shuguo 时间: 2013-11-21 11:51
for the kick back noise of bandgap， u may use RC to reduce (buffer is high current consumed)
for the noisy power ，u need a high psrr bandgap at about 40-50dB@ripple frequency,and power decouple cap is necessary。as to layout u need seperated the power line of digital and bandgap。 above solution is enough ，u do not need so many redundancy circit block cause of not much improvement and current consumption。作者: jiang_shuguo 时间: 2013-11-21 11:58
and how about your bandgap output resistance vs frequency ?作者: whb610 时间: 2013-11-21 13:13 回复 16#jiang_shuguo
由于纹波的频率是数字电路的瞬态动作造成的，因此没有一个固定的频率，只能估计，由于纹波上冲或者下降的频率也就是在几个n秒之间，所以纹波的主要频率成分用过快到GHz了吧，在这个频率下bandgap做到40~50db的电源抑制没有可能，bandgap的单位增益带宽好像也就是在几十K到几百K之间，何况我的bandgap还要求低功耗；bandgap输出电阻是700多K作者: jiang_shuguo 时间: 2013-11-21 13:28
u first figure out some concept,the giger Hz noise and low fre noise is killed out by decoulpe cap and high psrr of bandgap,only the medium fre is you care about.and the medium fre psrr of bandgap is not only depend on bandwith of bandgap.you first figure out the psrr of bandgap of all the fre.作者: whb610 时间: 2013-11-21 13:29 回复 16#jiang_shuguo
作者: jiang_shuguo 时间: 2013-11-21 13:29
and the solution is better enough to resolve your issue作者: jiang_shuguo 时间: 2013-11-21 13:35
is there any strict limit of area ? maybe the area is the cost.作者: jiang_shuguo 时间: 2013-11-21 13:37
you also need to check the output resistance of bandgap vs fre ,and how to figure it作者: jiang_shuguo 时间: 2013-11-21 13:38
you only give the dc output resistance of bandgap ,and it is useless.作者: jiang_shuguo 时间: 2013-11-21 13:42
if u have depletion nmos available ,the ripple of power is to be unvisibility by another solution作者: whb610 时间: 2013-11-21 14:07 回复 22#jiang_shuguo
我在bandgap输出端加5u：5u m=100的nmos电容仿真了一下PSRR，在10Hz以下，60db，35M以上，34db，10Hz~35MHz之间最小20db，中频的电源抑制很不满意啊，高频电源抑制也小了一点；也加纹波仿了一下瞬态，高频时bandgap输出端纹波大概在10mV的幅度，比我预想的要好，但是幅度还是太大大，这个在实测恐怕要超过2%，并且在数字电路的干扰下很难说实际应用中没有中频纹波； 输出电阻不能更小了，原因就在于低功耗，我给你的输出电阻值就是bandgap的输出支路上输出对地的电阻，对电源是pmos的电流源，这个可以认为阻值远大于对地电阻，忽略了；我要降低输出电阻值就只能增加整个bandgap的功耗作者: jiang_shuguo 时间: 2013-11-21 14:15
you need special care about the pst of medium fre .there also need a R before nmos cap ,but this R will affect you psr worst and trans result better. the output restance of bandgap is the whole of bandgap system not one branch.you leave the bandgap loop behand you head!作者: jiang_shuguo 时间: 2013-11-21 14:18
So now we ture our mind ,Do u have depletion nmos? i guess u have(process of soc chip always take depletion nmos available.)作者: jiang_shuguo 时间: 2013-11-21 14:19
So now we turn our mind ,Do u have depletion nmos? i guess u have(process of soc chip always take depletion nmos available.)
sorry about some spelling mistake!作者: whb610 时间: 2013-11-21 14:23 回复 24#jiang_shuguo
还有一点就是增加如此大的电阻，上电建立时间很长，500u秒之达到960mv，这个不符合要求了，差很远，我们要求是100us；现在的问题是PSRR最差的点就在16k，这样的话我最差也要加3M电阻才能使得中频电源抑制比降下来，加5M才达到我比较满意的程度；如果要把最差PSRR的点向高频方向推只能增加功耗，也不符合需求，很难办啊作者: jiang_shuguo 时间: 2013-11-21 14:57
u may focus on high psrr bandgap architecture,can u show us your bandgap schematic.作者: whb610 时间: 2013-11-21 14:57 回复 31#whb610
作者: jiang_shuguo 时间: 2013-11-21 15:14
the design process is not yours . you are trying error. have you consider how RC affect the psr,the trans response,the stbility of bandgap? the critical value of RC for above terms? this is not a easy work, but you just try little condition to make conlution !作者: whb610 时间: 2013-11-21 16:09 回复 36#jiang_shuguo
suggest u change architecture of bandgap. using kuijk cell. do your company have some reference circuit for you ? the 3sigma of this structure of bandgap is so big . it will out of your control ! and what about your triming method ?作者: jiang_shuguo 时间: 2013-11-21 16:46
here is 0.5uA below for ibias,2uA for op ,2uA or more for bjt branch.作者: jiang_shuguo 时间: 2013-11-21 16:51
for u area is the last consideration,cause you must perform the basic function and fill the spec.and then try to reduce area in case not severely affact function and performence.作者: whb610 时间: 2013-11-21 16:53 回复 38#semico_ljj
很不好意思的告诉您我没见过你说的kuijk cell，能提供资料吗，就算不能用也能学习一下啊 再次不好意思的告诉您，我们没有trimming手段，这个bandgap是给flash用的，trimming数据只能储存在flash中（加OTP或者激光修复我都不敢想，一巴掌就给扇回来），这就成了鸡生蛋蛋生鸡的问题了作者: jiang_shuguo 时间: 2013-11-21 17:21
if trimming not available ，u must use kuijk cell（op+pnp）作者: whb610 时间: 2013-11-21 17:39
if trimming not available ，u must use kuijk cell（op+pnp）
jiang_shuguo 发表于 2013-11-21 17:21
请问为什么没修复的话必须op+pnp的结构，我现在用的结构实际偏差会比较大吗，为什么会偏差比较大
请问是所有的op+pnp结构的bandgap都叫kuijk cell吗，谢谢作者: jiang_shuguo 时间: 2013-11-21 19:30
it just a name, your structure is banba cell. cause banba cell have no loop gain to supress offset。作者: hszgl 时间: 2013-11-21 19:32 本帖最后由 hszgl 于 2013-11-21 19:36 编辑
