The following steps describe the most common sequence for floorplanning:
1. Importing the design.
2. Studying the design’s connectivity.
3. Performing the minimum amount of floorplanning based on the chip design floorplan, or
do no floorplanning at all.
4. In some cases, no floorplanning is required. For example, a front-end designer might
want to predict the quality of the design’s netlist by initially placing the entire design
without any floorplanning. This iteration provides a good indication of how the blocks
should be located and arranged together with the larger modules. After a few iterations,
it should be clear how to position the blocks and modules in the floorplan.作者: damonzhao 时间: 2012-7-20 09:40
怎么不理解？作者: wenjg76 时间: 2012-7-20 10:55 回复 2#damonzhao
恩，工具给出的参考floorplan肯定考虑到了后面的时序收敛，
所以，如果我们能基于这个参考作改动（尽量小的），工具肯定是很高兴的
谢谢版主的及时回复作者: joemool 时间: 2012-7-27 21:25
Could you tell me which EDI version you have?
Seems like it is an old UG.
I will check the latest one to find if there are any confusing lines.作者: wenjg76 时间: 2012-10-20 01:01 本帖最后由 wenjg76 于 2012-10-20 01:07 编辑
