Digital Design/Verification Engineer Responsibility:
1)Understand functional spec and architecture, and implement design with Verilog.
2)Build testbench, monitors and testcases for DUT.
3)Simulate and debug design from module level to top level.
4)Go through FE design flow(synthesis, timing analysis, formal verification etc).
5)Help and give advice to BE flow. Requirements:
1)BS or above in Microelectronics-related fields.
2)Proficient on Verilog with good coding style.
3)Familiar with EDA tools like VCS/NC, DC, PT, Formality and etc..
4)Experience with shell/perl/tcl programming in linux.
5)Good communication skills (both written and oral in English and Mandarin).
6)Having FPGA experience, high level verification skills or BE flow knowledge is a plus.
7)Will be a big plus if having HDMI/DisplayPort experience.
Back-End Design Engineer Responsibility:
1)Take charge of back-end flow from netlist to GDS.
2)IP integration and information extraction.
3)Perform ECO and final check. Requirements:
1)BS or above in Microelectronics-related fields.
2)Expertise in sub-macro backend design(floorplan, CTS, PnR, DRC and etc.).
3)Experience in synopsys/cadence design tools.
4)Strong timing closing, power optimizing capabilities.
5)Good communication skills (both written and oral in English and Mandarin).
6)Experience in DFT is a plus.作者: qy79 时间: 2012-2-10 15:43
顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶作者: s20050430 时间: 2012-2-13 10:53 回复 2#qy79