标题: [ebook]The Power of Assertions in SystemVerilog [打印本页] 作者: pipiw 时间: 2010-11-17 10:37 标题: [ebook]The Power of Assertions in SystemVerilog 本帖最后由 pipiw 于 2010-11-17 13:10 编辑
[size=120%]The Power of Assertions in SystemVerilog
By Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
Publisher: Springer
Number Of Pages: 544
Publication Date: 2010-10-22
ISBN-10 / ASIN: 1441965998
ISBN-13 / EAN: 9781441965998
Product Description:
This book provides a deeper understanding of the meaning of the enhancements contained in the new SystemVerilog 1800-2009 LRM. In particular, it discusses the context of practical deployment in hardware design projects. The material also addresses language implementation alternatives and their impact on simulation performanceas well as the ability to debug them in simulation and formal verification environments. The underlying performance issues are illustrated for practical examples drawn from the author's experience.作者: mtwumtwu 时间: 2010-11-17 11:10
good reference for hardware design作者: zh123456789 时间: 2010-11-17 18:25
谢谢啊作者: qptom 时间: 2010-11-17 19:44
thanks!作者: wangzt 时间: 2010-11-17 19:45 回复 1#pipiw